7e3b3dd258
Instead of hardcoded definitions from soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
57 lines
1.2 KiB
C
57 lines
1.2 KiB
C
/*
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* Copyright (c) 2022 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_pinctrl
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
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#include <soc.h>
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#define MAX_PIN_NUM DT_PROP(DT_INST_PARENT(0), ngpios)
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#define PINCTRL_BASE_ADDR DT_INST_REG_ADDR(0)
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#define PINCTRL_IOF_EN (PINCTRL_BASE_ADDR + 0x0)
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#define PINCTRL_IOF_SEL (PINCTRL_BASE_ADDR + 0x4)
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static int pinctrl_sifive_set(uint32_t pin, uint32_t func)
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{
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uint32_t val;
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if (func > SIFIVE_PINMUX_IOF1 || pin >= MAX_PIN_NUM) {
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return -EINVAL;
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}
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val = sys_read32(PINCTRL_IOF_SEL);
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if (func == SIFIVE_PINMUX_IOF1) {
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val |= (SIFIVE_PINMUX_IOF1 << pin);
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} else {
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val &= ~(SIFIVE_PINMUX_IOF1 << pin);
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}
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sys_write32(val, PINCTRL_IOF_SEL);
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/* Enable IO function for this pin */
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val = sys_read32(PINCTRL_IOF_EN);
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val |= BIT(pin);
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sys_write32(val, PINCTRL_IOF_EN);
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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int i;
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for (i = 0; i < pin_cnt; i++) {
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pinctrl_sifive_set(pins[i].pin, pins[i].iof);
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}
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return 0;
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}
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