b53f62d259
Add support for interrupt driven MSI-X PVM feature for Viper. Function mask bit update is tracked with snoop interrupt and vector mask bit update is tracked with pcie pmon lite address range access detection interrupt. Both the interrupts are required to enable this feature. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
372 lines
12 KiB
C
372 lines
12 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_REGS_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_REGS_H_
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struct paxb_64 {
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uint32_t lower;
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uint32_t upper;
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};
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#ifdef CONFIG_PCIE_EP_IPROC_V2
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struct paxb_imap {
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uint32_t lower;
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uint32_t upper;
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uint32_t axim_write_config;
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uint32_t axim_read_config;
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};
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struct iproc_pcie_reg {
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uint32_t paxb_clk_control;
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uint32_t paxb_ep_perst_hold_off;
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uint32_t paxb_global_control;
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uint32_t paxb_flush_control;
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uint32_t paxb_flush_status;
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uint32_t paxb_strap_status;
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uint32_t paxb_reset_status;
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uint32_t paxb_mps_mrrs_stat;
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uint32_t paxb_cfg_addr;
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uint32_t paxb_cfg_data;
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uint32_t paxb_cfg_be;
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uint32_t paxb_config_ind_addr;
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uint32_t paxb_config_ind_data;
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uint32_t paxb_config_ind_cmpl_stat;
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uint32_t paxb_config_ind_be;
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uint32_t paxb_config_ecm_addr;
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uint32_t paxb_config_ecm_data;
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uint32_t paxb_hide_func_cfg;
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uint32_t paxb_0_apb_timeout;
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uint32_t paxb_0_apb_err_en_for_cfg_rd_cmpl;
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uint32_t paxb_0_apb_err_en_for_cfg_wr_cmpl;
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uint32_t paxb_0_ur_resp_on_apb_timeout;
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uint32_t paxb_0_crs_resp_on_flr_in_progress;
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uint32_t paxb_0_apb_read_data_on_ca;
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uint32_t paxb_0_apb_read_data_on_crs;
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uint32_t paxb_0_compare_bus_num_for_pf;
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uint32_t paxb_0_latch_bus_number_on_cfg_wr;
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uint32_t paxb_0_issue_slave_error_from_ple_on_ur;
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uint32_t paxb_0_ep_ple_cfg_register_0;
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uint32_t paxb_0_ep_ple_cfg_register_1;
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uint32_t paxb_0_ep_ple_cfg_register_2;
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uint32_t paxb_0_ep_ple_cfg_register_3;
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uint32_t paxb_0_ep_ple_cfg_register_4;
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uint32_t paxb_ordering_cfg;
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uint32_t paxb_master_cfg;
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uint32_t paxb_master_axid_seq_num_cfg;
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uint32_t paxb_pnpn_so_traffic_shaper_count_slow;
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uint32_t paxb_pnpn_so_traffic_shaper_count_fast;
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uint32_t paxb_pnpn_so_traffic_shaper_thrshold;
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uint32_t paxb_bdf_to_func_num_mapping;
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uint32_t paxb_atomics_cfg;
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uint32_t paxb_master_gic_its_address;
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uint32_t paxb_master_id_seq_num_avbl_status;
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uint32_t paxb_axim_rd_fsm_state;
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uint32_t paxb_atomics_status;
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uint32_t paxb_atomics_fail_addr_h_status;
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uint32_t paxb_atomics_fail_addr_l_status;
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uint32_t paxb_atomics_fail_status;
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uint32_t paxb_atomics_fail_pf_vf_num;
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uint32_t paxb_nullified_tx_pd_status;
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uint32_t paxb_nullified_tx_pd_addr_h_status;
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uint32_t paxb_nullified_tx_pd_addr_l_status;
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uint32_t paxb_ds_non_posted_crdt_default;
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uint32_t paxb_ds_posted_crdt_default;
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uint32_t paxb_ds_cmpl_crdt_default;
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uint32_t paxb_ds_cfg;
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uint32_t paxb_us_cfg;
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uint32_t paxb_axim_write_config_func0;
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uint32_t paxb_axim_read_config_func0;
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uint32_t paxb_axim_write_config_func1;
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uint32_t paxb_axim_read_config_func1;
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uint32_t paxb_axim_write_config_func2;
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uint32_t paxb_axim_read_config_func2;
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uint32_t paxb_axim_write_config_func3;
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uint32_t paxb_axim_read_config_func3;
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uint32_t paxb_axim_write_config_func4;
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uint32_t paxb_axim_read_config_func4;
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uint32_t paxb_axim_write_config_func5;
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uint32_t paxb_axim_read_config_func5;
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uint32_t paxb_axim_write_config_func6;
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uint32_t paxb_axim_read_config_func6;
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uint32_t paxb_axim_write_config_func7;
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uint32_t paxb_axim_read_config_func7;
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uint32_t paxb_axim_write_config_func8;
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uint32_t paxb_axim_read_config_func8;
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uint32_t paxb_axim_write_config_func9;
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uint32_t paxb_axim_read_config_func9;
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uint32_t paxb_axim_write_config_func10;
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uint32_t paxb_axim_read_config_func10;
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uint32_t paxb_axim_write_config_func11;
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uint32_t paxb_axim_read_config_func11;
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uint32_t paxb_axim_write_config_func12;
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uint32_t paxb_axim_read_config_func12;
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uint32_t paxb_axim_write_config_func13;
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uint32_t paxb_axim_read_config_func13;
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uint32_t paxb_axim_write_config_func14;
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uint32_t paxb_axim_read_config_func14;
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uint32_t paxb_axim_write_config_func15;
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uint32_t paxb_axim_read_config_func15;
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uint32_t paxb_default_imap_lower;
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uint32_t paxb_default_imap_upper;
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uint32_t paxb_default_imap_axim_write_config;
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uint32_t paxb_default_imap_axim_read_config;
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struct paxb_imap paxb_func0_imap0[8];
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struct paxb_imap paxb_func0_imap1[8];
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struct paxb_imap paxb_func0_imap2;
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struct paxb_imap paxb_func0_imap3[8];
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struct paxb_imap paxb_func0_imap4[8];
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struct paxb_64 paxb_iarr[5];
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uint32_t paxb_override_window0_cfg0;
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uint32_t paxb_override_window0_cfg1;
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uint32_t paxb_override_window0_write_cfg;
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uint32_t paxb_override_window0_read_cfg;
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uint32_t paxb_override_window1_cfg0;
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uint32_t paxb_override_window1_cfg1;
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uint32_t paxb_override_window1_write_cfg;
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uint32_t paxb_override_window1_read_cfg;
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uint32_t paxb_msi_base_addr_cfg;
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uint32_t paxb_msi_high_addr_cfg;
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uint32_t paxb_msi_window_write_cfg;
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uint32_t paxb_oarr_func0_msi_page;
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uint32_t paxb_oarr_func0_msi_page_upper;
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struct paxb_64 paxb_oarr[2];
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struct paxb_64 paxb_omap[2];
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struct paxb_64 paxb_oarr_2;
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struct paxb_64 paxb_omap_2;
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struct paxb_64 paxb_oarr_3;
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struct paxb_64 paxb_omap_3;
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struct paxb_64 paxb_oarr_4;
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uint32_t paxb_omap_4_upper;
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struct paxb_64 paxb_oarr_5;
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struct paxb_64 paxb_omap_5;
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struct paxb_64 paxb_omap_5_0;
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struct paxb_64 paxb_omap_5_1;
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struct paxb_64 paxb_omap_5_2;
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struct paxb_64 paxb_omap_5_3;
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struct paxb_64 paxb_omap_5_4;
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struct paxb_64 paxb_omap_5_5;
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struct paxb_64 paxb_omap_5_6;
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struct paxb_64 paxb_omap_5_7;
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uint32_t paxb_rc_pm_control;
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uint32_t paxb_rc_pm_status;
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uint32_t paxb_ep_pm_control;
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uint32_t paxb_ep_pm_status;
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uint32_t paxb_ep_ltr_control;
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uint32_t paxb_ep_ltr_status;
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uint32_t paxb_ep_obff_status;
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uint32_t paxb_pcie_error_status;
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uint32_t paxb_pcie_link_status;
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uint32_t paxb_ecam_cfg_0;
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uint32_t paxb_ecam_cfg_1;
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uint32_t paxb_ecam_cfg_rc;
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uint32_t paxb_ecam_crs_cfg;
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uint32_t paxb_ecam_cfg_rd_data;
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uint32_t paxb_ecam_cmpl_stat;
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uint32_t paxb_ecam_apb_err_cfg;
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uint32_t paxb_ecam_apb_ur_resp_cfg;
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uint32_t paxb_mem_pwr_cfg;
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uint32_t paxb_mem_iso_cfg;
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uint32_t paxb_mem_pwr_status;
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uint32_t paxb_free_cid_cfg;
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uint32_t paxb_free_cid_status;
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uint32_t paxb_slave_cfg;
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uint32_t paxb_slave_pf_vf_offset;
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uint32_t paxb_cmp_err_tx_cplh_status;
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uint32_t paxb_cmp_err_tx_cplh_addr_h_status;
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uint32_t paxb_cmp_err_tx_cplh_addr_l_status;
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uint32_t paxb_axi_slave_debug_status;
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uint32_t paxb_paxb_intr_status;
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uint32_t paxb_paxb_intr_en;
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uint32_t paxb_paxb_intr_clear;
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uint32_t paxb_rc_intr_clear_en;
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uint32_t paxb_rc_intr_status;
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uint32_t paxb_rc_intr_mask;
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uint32_t paxb_rc_intr_clear;
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uint32_t paxb_pcie_cfg_intr_status;
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uint32_t paxb_pcie_cfg_intr_mask;
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uint32_t paxb_pcie_cfg_intr_clear;
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uint32_t paxb_master_intr_status;
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uint32_t paxb_master_intr_mask;
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uint32_t paxb_master_intr_clear;
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uint32_t paxb_slave_intr_status;
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uint32_t paxb_slave_intr_mask;
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uint32_t paxb_slave_intr_clear;
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uint32_t paxb_user_if_intr_status;
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uint32_t paxb_user_if_intr_mask;
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uint32_t paxb_user_if_intr_clear;
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uint32_t paxb_master_underflow_status;
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uint32_t paxb_master_overflow_status;
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uint32_t paxb_master_fifo_ecc_corr_status;
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uint32_t paxb_master_fifo_ecc_uncorr_status;
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uint32_t paxb_slave_underflow_status;
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uint32_t paxb_slave_overflow_status;
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uint32_t paxb_slave_ecc_err_corrected_status;
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uint32_t paxb_slave_ecc_err_uncor_status;
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uint32_t paxb_userif_underflow_status;
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uint32_t paxb_userif_overflow_status;
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uint32_t paxb_userif_ecc_err_corrected_status;
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uint32_t paxb_userif_ecc_err_uncor_status;
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uint32_t paxb_msg_status;
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uint32_t paxb_msg_header[4];
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uint32_t paxb_msg_data[8];
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uint32_t paxb_msg_control;
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uint32_t paxb_msg_drop_control;
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uint32_t paxb_snoop_addr_cfg[4];
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};
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#else
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struct iproc_pcie_reg {
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uint32_t paxb_clk_control;
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uint32_t paxb_rc_pm_control;
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uint32_t paxb_rc_pm_status;
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uint32_t paxb_ep_pm_control;
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uint32_t paxb_ep_pm_status;
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uint32_t paxb_ep_ltr_control;
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uint32_t paxb_ep_ltr_status;
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uint32_t paxb_reserved_0[1];
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uint32_t paxb_ep_obff_status;
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uint32_t paxb_pcie_error_status;
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uint32_t paxb_reserved_1[2];
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uint32_t paxb_paxb_endianness;
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uint32_t paxb_apb_timeout_count;
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uint32_t paxb_paxb_tx_arbiter_priority;
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uint32_t paxb_reserved_2[1];
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uint32_t paxb_paxb_rd_cmpl_buf_init_start;
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uint32_t paxb_paxb_rd_cmpl_buf_init_done;
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uint32_t paxb_pcie_ordering_rules_enable;
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uint32_t paxb_axi_slverr_en_for_mem_rd_cmpl;
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uint32_t paxb_reserved_3[44];
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uint32_t paxb_pcie_rc_axi_config;
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uint32_t paxb_pcie_ep_axi_config;
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uint32_t paxb_pcie_paxb_rx_debug_status_0;
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uint32_t paxb_pcie_paxb_rx_debug_control_0;
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uint32_t paxb_reserved_4[4];
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uint32_t paxb_config_ind_addr;
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uint32_t paxb_config_ind_data;
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uint32_t paxb_reserved_5[51];
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uint32_t paxb_cfg_be;
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uint32_t paxb_cfg_addr;
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uint32_t paxb_cfg_data;
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uint32_t paxb_pcie_sys_eq_page;
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uint32_t paxb_pcie_sys_msi_page;
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uint32_t paxb_reserved_6[2];
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uint32_t paxb_pcie_sys_msi_ctrl[6];
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uint32_t paxb_reserved_7[10];
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uint32_t paxb_pcie_sys_eq_head_0;
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uint32_t paxb_pcie_sys_eq_tail_0;
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uint32_t paxb_pcie_sys_eq_head_1;
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uint32_t paxb_pcie_sys_eq_tail_1;
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uint32_t paxb_pcie_sys_eq_head_2;
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uint32_t paxb_pcie_sys_eq_tail_2;
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uint32_t paxb_pcie_sys_eq_head_3;
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uint32_t paxb_pcie_sys_eq_tail_3;
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uint32_t paxb_pcie_sys_eq_head_4;
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uint32_t paxb_pcie_sys_eq_tail_4;
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uint32_t paxb_pcie_sys_eq_head_5;
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uint32_t paxb_pcie_sys_eq_tail_5;
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uint32_t paxb_pcie_sys_eq_tail_early[6];
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uint32_t paxb_reserved_8[2];
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uint32_t paxb_pcie_sys_eq_overwritten[6];
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uint32_t paxb_reserved_9[2];
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uint32_t paxb_pcie_sys_eq_page_upper;
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uint32_t paxb_pcie_sys_msi_page_upper;
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uint32_t paxb_reserved_10[26];
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uint32_t paxb_pcie_sys_rc_intx_en;
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uint32_t paxb_pcie_sys_rc_intx_csr;
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uint32_t paxb_reserved_11[2];
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uint32_t paxb_pcie_sys_msi_req;
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uint32_t paxb_pcie_sys_host_intr_en;
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uint32_t paxb_pcie_sys_host_intr_csr;
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uint32_t paxb_reserved_12[1];
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uint32_t paxb_pcie_sys_host_intr[4];
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uint32_t paxb_pcie_sys_ep_int_en0;
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uint32_t paxb_pcie_sys_ep_int_en1;
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uint32_t paxb_reserved_13[2];
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uint32_t paxb_pcie_sys_ep_int_csr0;
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uint32_t paxb_pcie_sys_ep_int_csr1;
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uint32_t paxb_reserved_14[2];
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uint32_t paxb_cmicd_to_pcie_intr_en;
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uint32_t paxb_reserved_15[543];
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uint32_t paxb_func0_imap0[8];
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uint32_t paxb_func1_imap0[8];
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uint32_t paxb_func0_imap0_upper[8];
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uint32_t paxb_func1_imap0_upper[8];
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uint32_t paxb_reserved_16[16];
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struct paxb_64 paxb_func0_imap2;
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struct paxb_64 paxb_func1_imap2;
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uint32_t paxb_func0_imap0_0123_regs_type;
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uint32_t paxb_reserved_17[11];
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struct paxb_64 paxb_iarr[3];
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uint32_t paxb_reserved_18[2];
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struct paxb_64 paxb_oarr[2];
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uint32_t paxb_reserved_19[1];
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uint32_t paxb_oarr_func0_msi_page;
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uint32_t paxb_oarr_func1_msi_page;
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uint32_t paxb_reserved_20[1];
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struct paxb_64 paxb_omap[2];
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uint32_t paxb_oarr_func0_msi_page_upper;
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uint32_t paxb_oarr_func1_msi_page_upper;
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uint32_t paxb_reserved_21[1];
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uint32_t paxb_func1_iarr_2_size;
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struct paxb_64 paxb_oarr_2;
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struct paxb_64 paxb_omap_2;
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struct paxb_64 paxb_func0_imap1[8];
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struct paxb_64 paxb_func1_imap1[8];
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struct paxb_64 paxb_oarr_3;
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struct paxb_64 paxb_omap_3;
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struct paxb_64 paxb_iarr_3;
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struct paxb_64 paxb_func0_imap3[8];
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uint32_t paxb_func0_imap3_axuser[8];
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struct paxb_64 paxb_iarr_4;
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struct paxb_64 paxb_func0_imap4[8];
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uint32_t paxb_func0_imap4_axuser[8];
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uint32_t paxb_default_imap_lower;
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uint32_t paxb_default_imap_upper;
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uint32_t paxb_default_imap_axuser;
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uint32_t paxb_default_imap_axcache;
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uint32_t paxb_cfg_tlp_rd_status;
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uint32_t paxb_reserved_22[7];
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uint32_t paxb_mem_control;
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uint32_t paxb_mem_ecc_err_log_0;
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uint32_t paxb_mem_ecc_err_log_1;
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uint32_t paxb_pcie_link_status;
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uint32_t paxb_strap_status;
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uint32_t paxb_reset_status;
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uint32_t paxb_reset_enable_in_pcie_link_down;
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uint32_t paxb_reserved_23[1];
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uint32_t paxb_paxb_tx_debug_cfg;
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uint32_t paxb_paxb_misc_config;
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uint32_t paxb_reserved_24[2];
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uint32_t paxb_paxb_intr_en;
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uint32_t paxb_paxb_intr_clear;
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uint32_t paxb_paxb_intr_status;
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uint32_t paxb_reserved_25[1];
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uint32_t paxb_apb_err_en_for_cfg_rd_cmpl;
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uint32_t paxb_pcie_replay_addr_buf_ecc_log;
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uint32_t paxb_pcie_replay_data_buf_ecc_log;
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uint32_t paxb_pcie_dl_to_tl_buf_ecc_log;
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uint32_t paxb_pcie_tl_to_dl_buf_ecc_log;
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uint32_t paxb_reserved_26[3];
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uint32_t paxb_func0_imap0_axuser[8];
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uint32_t paxb_func1_imap0_axuser[8];
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uint32_t paxb_func0_imap1_axuser[8];
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|
uint32_t paxb_func1_imap1_axuser[8];
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uint32_t paxb_func0_imap2_axuser;
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|
uint32_t paxb_func1_imap2_axuser;
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};
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#endif
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static inline void pcie_write32(uint32_t data, uint32_t *addr)
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{
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sys_write32(data, (mem_addr_t)addr);
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}
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static inline uint32_t pcie_read32(uint32_t *addr)
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|
{
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return sys_read32((mem_addr_t)addr);
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}
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_EP_IPROC_REGS_H_ */
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