d628bfc148
There is no smartdma on RT700, so to perform DCS memory write the CPU has to write APB buffer word by word, which is too slow for most applications. But the DCNano in DBI mode can be used to interface with the MIPI-DSI on RT700, and send data to MIPI-DSI to transfer, once it is properly configured, which solves the issue. First added new parameter first_write in display_buffer_descriptor to let NXP DCNano DBI driver know to use MIPI_DCS_WRITE_MEMORY_START or MIPI_DCS_WRITE_MEMORY_CONTINUE. Second updated the MCUX MIPI-DSI driver to support using the NXP DCNano DBI driver for memory write. Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
45 lines
1.2 KiB
Text
45 lines
1.2 KiB
Text
# Copyright 2022-2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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config MIPI_DSI_MCUX
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bool "NXP MCUX MIPI-DSI Host Controller"
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default y
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depends on DT_HAS_NXP_IMX_MIPI_DSI_ENABLED
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help
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NXP MIPI DSI controller driver
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config MIPI_DSI_MCUX_2L
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bool "NXP MCUX MIPI-DSI 2L Controller"
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default y
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depends on DT_HAS_NXP_MIPI_DSI_2L_ENABLED
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help
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NXP MIPI DSI 2L controller driver
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if MIPI_DSI_MCUX_2L
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config MIPI_DSI_MCUX_2L_SMARTDMA
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bool "Use smartDMA controller with MIPI DSI"
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default y
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depends on DMA_MCUX_SMARTDMA
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help
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Use SMARTDMA. This accelerator will automatically
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convert RGB565 input data to BGR565 (little endian to big endian),
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and write it to the MIPI DSI.
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config MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
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bool "Use NXP DCNano DBI controller with MIPI DSI"
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default y
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depends on DT_HAS_NXP_MIPI_DBI_DCNANO_LCDIF_ENABLED
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select MIPI_DBI
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help
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Use DCNano DBI controller for the data transfer.
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config MIPI_DSI_MCUX_2L_SWAP16
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bool "Swap 16 byte color"
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help
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Swap 16 byte color data from little to big endian format. When
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this Kconfig is enabled, the DSI expects RGB565 data in little endian
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format, which will then be byte swapped.
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endif # MIPI_DSI_MCUX_2L
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