83f89da24e
FMC default clock is hclk, it may affected by sys_ck change. Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(memc_stm32, CONFIG_MEMC_LOG_LEVEL);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_fmc)
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#define DT_DRV_COMPAT st_stm32_fmc
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_fmc)
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#define DT_DRV_COMPAT st_stm32h7_fmc
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#else
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#error "No compatible FMC devicetree node found"
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#endif
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/* This symbol takes the value 1 if one of the device instances */
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/* is configured in dts with a domain clock */
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_FMC_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_FMC_DOMAIN_CLOCK_SUPPORT 0
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#endif
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struct memc_stm32_config {
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uint32_t fmc;
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const struct stm32_pclken *pclken;
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size_t pclk_len;
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const struct pinctrl_dev_config *pcfg;
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};
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static int memc_stm32_init(const struct device *dev)
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{
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const struct memc_stm32_config *config = dev->config;
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int r;
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const struct device *clk;
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/* configure pinmux */
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r = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (r < 0) {
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LOG_ERR("FMC pinctrl setup failed (%d)", r);
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return r;
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}
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/* enable FMC peripheral clock */
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clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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if (!device_is_ready(clk)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]);
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if (r < 0) {
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LOG_ERR("Could not initialize FMC clock (%d)", r);
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return r;
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}
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if (IS_ENABLED(STM32_FMC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
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/* Enable FMC clock source */
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r = clock_control_configure(clk, (clock_control_subsys_t)&config->pclken[1], NULL);
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if (r < 0) {
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LOG_ERR("Could not select FMC clock (%d)", r);
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return r;
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}
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}
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_fmc)
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#if (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 1)
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/* sdram-sram */
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MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_0);
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#elif (DT_ENUM_IDX(DT_DRV_INST(0), st_mem_swap) == 2)
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/* sdramb2 */
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MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, FMC_BCR1_BMAP_1);
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#endif
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#endif
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return 0;
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}
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PINCTRL_DT_INST_DEFINE(0);
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static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0);
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static const struct memc_stm32_config config = {
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.fmc = DT_INST_REG_ADDR(0),
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.pclken = pclken,
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.pclk_len = DT_INST_NUM_CLOCKS(0),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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};
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DEVICE_DT_INST_DEFINE(0, memc_stm32_init, NULL, NULL,
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&config, POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY, NULL);
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