87f3e331a6
Add support for I2S domain clock for STM32 devices. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
62 lines
1.2 KiB
C
62 lines
1.2 KiB
C
/*
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* Copyright (c) 2018 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32_I2S_H_
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#define _STM32_I2S_H_
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struct queue_item {
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void *mem_block;
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size_t size;
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};
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/* Minimal ring buffer implementation */
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struct ring_buf {
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struct queue_item *buf;
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uint16_t len;
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uint16_t head;
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uint16_t tail;
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};
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/* Device constant configuration parameters */
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struct i2s_stm32_cfg {
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SPI_TypeDef *i2s;
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const struct stm32_pclken *pclken;
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size_t pclk_len;
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const struct pinctrl_dev_config *pcfg;
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void (*irq_config)(const struct device *dev);
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bool master_clk_sel;
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};
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struct stream {
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int32_t state;
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struct k_sem sem;
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const struct device *dev_dma;
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uint32_t dma_channel;
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struct dma_config dma_cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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uint8_t fifo_threshold;
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struct i2s_config cfg;
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struct ring_buf mem_block_queue;
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void *mem_block;
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bool last_block;
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bool master;
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int (*stream_start)(struct stream *, const struct device *dev);
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void (*stream_disable)(struct stream *, const struct device *dev);
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void (*queue_drop)(struct stream *);
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};
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/* Device run time data */
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struct i2s_stm32_data {
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struct stream rx;
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struct stream tx;
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};
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#endif /* _STM32_I2S_H_ */
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