cbb6c2886a
i2s driver have not suooprt frdm_mcxn947 pll clk set. so add macro CONFIG_I2S_HAS_PLL_SETTING to control pll init. Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
35 lines
654 B
Text
35 lines
654 B
Text
# MCUX I2S driver configuration options
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# Copyright 2021,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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menuconfig I2S_MCUX_SAI
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bool "NXP MCUX I2S controller driver"
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default y
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depends on DT_HAS_NXP_MCUX_I2S_ENABLED
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select DMA
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select PINCTRL
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help
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Enable I2S support on the I.MX family of processors.
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if I2S_MCUX_SAI
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config I2S_RX_BLOCK_COUNT
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int "RX queue length"
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default 4
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config I2S_TX_BLOCK_COUNT
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int "TX queue length"
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default 4
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config I2S_EDMA_BURST_SIZE
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int "I2S EDMA BURST SIZE"
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default 2
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help
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I2S EDMA burst size in bytes.
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config I2S_HAS_PLL_SETTING
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bool "I2S will setting pll in driver"
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default y
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endif # I2S_MCUX_SAI
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