ca33905248
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
73 lines
2.8 KiB
C
73 lines
2.8 KiB
C
/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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*
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* Driver private data declarations, GPIO bank module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
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#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
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/*
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* Register address calculation macros
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* Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
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*/
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#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_conf->base_addr\
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+ ((uint32_t)dev_conf->bank_index * 0x8))
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#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\
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+ ((uint32_t)dev_conf->bank_index * 0x8))
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#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\
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+ ((uint32_t)dev_conf->bank_index * 0x4))
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#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\
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+ ((uint32_t)dev_conf->bank_index * 0x4))
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#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_conf->base_addr + 0x20C)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_conf->base_addr + 0x210)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_conf->base_addr + 0x214)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_conf->base_addr + 0x218)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_conf->base_addr + 0x21C)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_conf->base_addr + 0x220)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_conf->base_addr + 0x224)\
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+ ((uint32_t)dev_conf->bank_index * 0x40))
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/**
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* @brief Run-time modifiable device data structure.
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*
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* This struct contains all data of a PS MIO / EMIO GPIO bank
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* which is modifiable at run-time, such as the configuration
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* parameters and current values of each individual pin belonging
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* to the respective bank.
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*/
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struct gpio_xlnx_ps_bank_dev_data {
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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};
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/**
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* @brief Constant device configuration data structure.
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*
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* This struct contains all data of a PS MIO / EMIO GPIO bank
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* which is required for proper operation (such as base memory
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* addresses etc.) which don't have to and therefore cannot be
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* modified at run-time.
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*/
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struct gpio_xlnx_ps_bank_dev_cfg {
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struct gpio_driver_config common;
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uint32_t base_addr;
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uint8_t bank_index;
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};
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#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ */
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