64968d7402
Only provide implementations for optional operations if needed. This patch deletes quite a few dummy `pin_interrupt_configure` ops (now optional), and adjusts ifdeffery on some drivers so that optional ops are only provided if they implement real functionality. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
404 lines
9 KiB
C
404 lines
9 KiB
C
/*
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* Copyright (c) 2020 Geanix ApS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mcp23s17
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_mcp23s17);
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/* Register definitions */
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#define REG_IODIR_PORTA 0x00
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#define REG_IODIR_PORTB 0x01
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#define REG_IPOL_PORTA 0x02
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#define REG_IPOL_PORTB 0x03
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#define REG_GPINTEN_PORTA 0x04
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#define REG_GPINTEN_PORTB 0x05
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#define REG_DEFVAL_PORTA 0x06
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#define REG_DEFVAL_PORTB 0x07
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#define REG_INTCON_PORTA 0x08
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#define REG_INTCON_PORTB 0x09
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#define REG_GPPU_PORTA 0x0C
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#define REG_GPPU_PORTB 0x0D
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#define REG_INTF_PORTA 0x0E
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#define REG_INTF_PORTB 0x0F
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#define REG_INTCAP_PORTA 0x10
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#define REG_INTCAP_PORTB 0x11
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#define REG_GPIO_PORTA 0x12
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#define REG_GPIO_PORTB 0x13
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#define REG_OLAT_PORTA 0x14
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#define REG_OLAT_PORTB 0x15
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#define MCP23S17_ADDR 0x40
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#define MCP23S17_READBIT 0x01
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/** Configuration data */
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struct mcp23s17_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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struct spi_dt_spec bus;
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};
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/** Runtime driver data */
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struct mcp23s17_drv_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data data;
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struct k_sem lock;
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struct {
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uint16_t iodir;
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uint16_t ipol;
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uint16_t gpinten;
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uint16_t defval;
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uint16_t intcon;
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uint16_t iocon;
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uint16_t gppu;
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uint16_t intf;
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uint16_t intcap;
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uint16_t gpio;
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uint16_t olat;
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} reg_cache;
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};
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static int read_port_regs(const struct device *dev, uint8_t reg,
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uint16_t *buf)
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{
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const struct mcp23s17_config *config = dev->config;
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int ret;
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uint16_t port_data;
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uint8_t addr = MCP23S17_ADDR | MCP23S17_READBIT;
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uint8_t buffer_tx[4] = { addr, reg, 0, 0 };
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const struct spi_buf tx_buf = {
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.buf = buffer_tx,
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.len = 4,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_buf[2] = {
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{
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.buf = NULL,
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.len = 2
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},
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{
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.buf = (uint8_t *)&port_data,
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.len = 2
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}
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};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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ret = spi_transceive_dt(&config->bus, &tx, &rx);
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if (ret) {
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LOG_DBG("spi_transceive FAIL %d\n", ret);
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return ret;
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}
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*buf = sys_le16_to_cpu(port_data);
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LOG_DBG("MCP23S17: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X",
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reg, (*buf & 0xFF), (reg + 1), (*buf >> 8));
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return 0;
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}
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static int write_port_regs(const struct device *dev, uint8_t reg,
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uint16_t value)
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{
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const struct mcp23s17_config *config = dev->config;
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int ret;
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uint16_t port_data;
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LOG_DBG("MCP23S17: Write: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X",
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reg, (value & 0xFF), (reg + 1), (value >> 8));
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port_data = sys_cpu_to_le16(value);
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uint8_t addr = MCP23S17_ADDR;
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uint8_t buffer_tx[2] = { addr, reg };
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const struct spi_buf tx_buf[2] = {
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{
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.buf = buffer_tx,
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.len = 2,
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},
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{
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.buf = (uint8_t *)&port_data,
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.len = 2,
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}
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};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = ARRAY_SIZE(tx_buf),
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};
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ret = spi_write_dt(&config->bus, &tx);
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if (ret) {
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LOG_DBG("spi_write FAIL %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags)
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{
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struct mcp23s17_drv_data *drv_data = dev->data;
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uint16_t *dir = &drv_data->reg_cache.iodir;
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uint16_t *output = &drv_data->reg_cache.gpio;
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int ret;
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if ((flags & GPIO_OUTPUT) != 0U) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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*output |= BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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*output &= ~BIT(pin);
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}
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*dir &= ~BIT(pin);
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} else {
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*dir |= BIT(pin);
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}
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ret = write_port_regs(dev, REG_GPIO_PORTA, *output);
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if (ret != 0) {
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return ret;
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}
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ret = write_port_regs(dev, REG_IODIR_PORTA, *dir);
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return ret;
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}
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static int setup_pin_pullupdown(const struct device *dev, uint32_t pin,
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int flags)
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{
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struct mcp23s17_drv_data *drv_data = dev->data;
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uint16_t port;
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int ret;
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/* Setup pin pull up or pull down */
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port = drv_data->reg_cache.gppu;
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/* pull down == 0, pull up == 1 */
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if ((flags & GPIO_PULL_DOWN) != 0U) {
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return -ENOTSUP;
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}
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WRITE_BIT(port, pin, (flags & GPIO_PULL_UP) != 0U);
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ret = write_port_regs(dev, REG_GPPU_PORTA, port);
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if (ret == 0) {
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drv_data->reg_cache.gppu = port;
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}
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return ret;
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}
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static int mcp23s17_config(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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struct mcp23s17_drv_data *drv_data = dev->data;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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if ((flags & GPIO_OPEN_DRAIN) != 0U) {
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ret = -ENOTSUP;
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goto done;
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}
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ret = setup_pin_dir(dev, pin, flags);
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if (ret) {
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LOG_ERR("MCP23S17: error setting pin direction (%d)", ret);
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goto done;
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}
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ret = setup_pin_pullupdown(dev, pin, flags);
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if (ret) {
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LOG_ERR("MCP23S17: error setting pin pull up/down (%d)", ret);
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goto done;
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}
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done:
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_get_raw(const struct device *dev, uint32_t *value)
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{
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struct mcp23s17_drv_data *drv_data = dev->data;
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uint16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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ret = read_port_regs(dev, REG_GPIO_PORTA, &buf);
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if (ret != 0) {
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goto done;
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}
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*value = buf;
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done:
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_set_masked_raw(const struct device *dev,
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uint32_t mask, uint32_t value)
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{
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struct mcp23s17_drv_data *drv_data = dev->data;
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uint16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->reg_cache.gpio;
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buf = (buf & ~mask) | (mask & value);
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ret = write_port_regs(dev, REG_GPIO_PORTA, buf);
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if (ret == 0) {
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drv_data->reg_cache.gpio = buf;
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}
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int mcp23s17_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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return mcp23s17_port_set_masked_raw(dev, mask, mask);
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}
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static int mcp23s17_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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return mcp23s17_port_set_masked_raw(dev, mask, 0);
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}
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static int mcp23s17_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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struct mcp23s17_drv_data *const drv_data =
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(struct mcp23s17_drv_data *const)dev->data;
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uint16_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->reg_cache.gpio;
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buf ^= mask;
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ret = write_port_regs(dev, REG_GPIO_PORTA, buf);
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if (ret == 0) {
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drv_data->reg_cache.gpio = buf;
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}
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static const struct gpio_driver_api api_table = {
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.pin_configure = mcp23s17_config,
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.port_get_raw = mcp23s17_port_get_raw,
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.port_set_masked_raw = mcp23s17_port_set_masked_raw,
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.port_set_bits_raw = mcp23s17_port_set_bits_raw,
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.port_clear_bits_raw = mcp23s17_port_clear_bits_raw,
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.port_toggle_bits = mcp23s17_port_toggle_bits,
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};
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static int mcp23s17_init(const struct device *dev)
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{
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const struct mcp23s17_config *config = dev->config;
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struct mcp23s17_drv_data *drv_data = dev->data;
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if (!spi_is_ready_dt(&config->bus)) {
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LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
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return -ENODEV;
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}
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k_sem_init(&drv_data->lock, 1, 1);
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return 0;
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}
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#define MCP23S17_INIT(inst) \
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static const struct mcp23s17_config mcp23s17_##inst##_config = { \
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.common = { \
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.port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
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}, \
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.bus = SPI_DT_SPEC_INST_GET( \
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inst, \
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SPI_OP_MODE_MASTER | SPI_MODE_CPOL | \
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SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
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}; \
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\
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static struct mcp23s17_drv_data mcp23s17_##inst##_drvdata = { \
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/* Default for registers according to datasheet */ \
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.reg_cache.iodir = 0xFFFF, \
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.reg_cache.ipol = 0x0, \
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.reg_cache.gpinten = 0x0, \
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.reg_cache.defval = 0x0, \
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.reg_cache.intcon = 0x0, \
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.reg_cache.iocon = 0x0, \
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.reg_cache.gppu = 0x0, \
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.reg_cache.intf = 0x0, \
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.reg_cache.intcap = 0x0, \
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.reg_cache.gpio = 0x0, \
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.reg_cache.olat = 0x0, \
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}; \
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\
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/* This has to init after SPI master */ \
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DEVICE_DT_INST_DEFINE(inst, mcp23s17_init, \
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NULL, \
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&mcp23s17_##inst##_drvdata, \
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&mcp23s17_##inst##_config, \
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POST_KERNEL, \
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CONFIG_GPIO_MCP23S17_INIT_PRIORITY, \
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&api_table);
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DT_INST_FOREACH_STATUS_OKAY(MCP23S17_INIT)
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