7795558ad5
For the flash driver, the base address is the MCU internal flash address (usually 0x8000000). This PR gets the that address from the device tree node "st,stm32-nv-flash" instead of relying on the CONFIG_FLASH_BASE_ADDRESS which might differ when building for another flash memory. Signed-off-by: Francois Ramu <francois.ramu@st.com>
418 lines
10 KiB
C
418 lines
10 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_DOMAIN flash_stm32l4
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <string.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include "flash_stm32.h"
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#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && \
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!defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) && \
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!defined(STM32L4Q5xx) && !defined(STM32L4P5xx)
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#define STM32L4X_PAGE_SHIFT 11
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#else
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#define STM32L4X_PAGE_SHIFT 12
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#endif
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#if defined(FLASH_OPTR_DUALBANK) || defined(FLASH_STM32_DBANK)
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#define CONTROL_DCACHE
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#endif
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_DCEN) {
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regs->ACR &= ~FLASH_ACR_DCEN;
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/* Datasheet: DCRST: Data cache reset
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* This bit can be written only when the data cache is disabled
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*/
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= ~FLASH_ACR_DCRST;
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regs->ACR |= FLASH_ACR_DCEN;
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}
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if (regs->ACR & FLASH_ACR_ICEN) {
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regs->ACR &= ~FLASH_ACR_ICEN;
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/* Datasheet: ICRST: Instruction cache reset :
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* This bit can be written only when the instruction cache
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* is disabled
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*/
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regs->ACR |= FLASH_ACR_ICRST;
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regs->ACR &= ~FLASH_ACR_ICRST;
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regs->ACR |= FLASH_ACR_ICEN;
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}
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}
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/*
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* STM32L4xx devices can have up to 512 2K pages on two 256x2K pages banks
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*
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* STM32L4R/Sxx devices can have up to 512 4K pages on two 256x4K pages banks
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*/
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static unsigned int get_page(off_t offset)
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{
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return offset >> STM32L4X_PAGE_SHIFT;
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}
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static int write_dword(const struct device *dev, off_t offset, uint64_t val)
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{
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volatile uint32_t *flash = (uint32_t *)(offset + FLASH_STM32_BASE_ADDRESS);
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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#ifdef CONTROL_DCACHE
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bool dcache_enabled = false;
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#endif /* CONTROL_DCACHE */
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uint32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash main memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Check if this double word is erased and value isn't 0.
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*
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* It is allowed to write only zeros over an already written dword
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* See 3.3.7 in reference manual.
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*/
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if ((flash[0] != 0xFFFFFFFFUL ||
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flash[1] != 0xFFFFFFFFUL) && val != 0UL) {
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LOG_ERR("Word at offs %ld not erased", (long)offset);
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return -EIO;
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}
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#ifdef CONTROL_DCACHE
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/*
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* Disable the data cache to avoid the silicon errata 2.2.3:
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* "Data cache might be corrupted during Flash memory read-while-write operation"
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*/
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if (regs->ACR & FLASH_ACR_DCEN) {
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dcache_enabled = true;
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regs->ACR &= (~FLASH_ACR_DCEN);
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}
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#endif /* CONTROL_DCACHE */
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/* Set the PG bit */
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regs->CR |= FLASH_CR_PG;
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/* Flush the register write */
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tmp = regs->CR;
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/* Perform the data write operation at the desired memory address */
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flash[0] = (uint32_t)val;
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flash[1] = (uint32_t)(val >> 32);
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(dev);
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/* Clear the PG bit */
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regs->CR &= (~FLASH_CR_PG);
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#ifdef CONTROL_DCACHE
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/* Reset/enable the data cache if previously enabled */
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if (dcache_enabled) {
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= (~FLASH_ACR_DCRST);
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regs->ACR |= FLASH_ACR_DCEN;
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}
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#endif /* CONTROL_DCACHE */
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return rc;
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}
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#define SOC_NV_FLASH_SIZE DT_REG_SIZE(DT_INST(0, soc_nv_flash))
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static int erase_page(const struct device *dev, unsigned int page)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t tmp;
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uint16_t pages_per_bank;
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int rc;
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#if !defined(FLASH_OPTR_DUALBANK) && !defined(FLASH_STM32_DBANK)
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/* Single bank device. Each page is of 2KB size */
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pages_per_bank = SOC_NV_FLASH_SIZE >> 11;
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#elif defined(FLASH_OPTR_DUALBANK)
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/* L4 series (2K page size) with configurable Dual Bank (default y) */
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/* Dual Bank is only option for 1M devices */
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if ((regs->OPTR & FLASH_OPTR_DUALBANK) ||
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(SOC_NV_FLASH_SIZE == (1024*1024))) {
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/* Dual Bank configuration (nbr pages = flash size / 2 / 2K) */
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pages_per_bank = SOC_NV_FLASH_SIZE >> 12;
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} else {
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/* Single bank configuration. This has not been validated. */
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/* Not supported for now. */
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return -ENOTSUP;
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}
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#elif defined(FLASH_STM32_DBANK)
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/* L4+ series (4K page size) with configurable Dual Bank (default y)*/
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if (regs->OPTR & FLASH_STM32_DBANK) {
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/* Dual Bank configuration (nbre pags = flash size / 2 / 4K) */
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pages_per_bank = SOC_NV_FLASH_SIZE >> 13;
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} else {
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/* Single bank configuration */
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/* Requires 128 bytes data read. This config is not supported */
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return -ENOTSUP;
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}
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#endif
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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flush_cache(regs);
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/* Set the PER bit and select the page you wish to erase */
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regs->CR |= FLASH_CR_PER;
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#ifdef FLASH_CR_BKER
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regs->CR &= ~FLASH_CR_BKER_Msk;
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/* Select bank, only for DUALBANK devices */
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if (page >= pages_per_bank)
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regs->CR |= FLASH_CR_BKER;
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#endif
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regs->CR &= ~FLASH_CR_PNB_Msk;
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regs->CR |= ((page % pages_per_bank) << 3);
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/* Set the STRT bit */
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regs->CR |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->CR;
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len)
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{
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int i, rc = 0;
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(dev, i);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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for (i = 0; i < len; i += 8, offset += 8U) {
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rc = write_dword(dev, offset,
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UNALIGNED_GET((const uint64_t *) data + (i >> 3)));
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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static __unused int write_optb(const struct device *dev, uint32_t mask,
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uint32_t value)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc;
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if (regs->CR & FLASH_CR_OPTLOCK) {
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return -EIO;
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}
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if ((regs->OPTR & mask) == value) {
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return 0;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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regs->OPTR = (regs->OPTR & ~mask) | value;
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regs->CR |= FLASH_CR_OPTSTRT;
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/* Make sure previous write is completed. */
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barrier_dsync_fence_full();
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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return 0;
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}
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#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
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/*
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* Remark for future development implementing Write Protection for the L4 parts:
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*
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* STM32L4 allows for 2 write protected memory areas, c.f. FLASH_WEP1AR, FLASH_WRP1BR
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* which are defined by their start and end pages.
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*
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* Other STM32 parts (i.e. F4 series) uses bitmask to select sectors.
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*
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* To implement Write Protection for L4 one should thus add a new EX_OP like
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* FLASH_STM32_EX_OP_SECTOR_WP_RANGED in stm32_flash_api_extensions.h
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*/
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#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
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int flash_stm32_update_rdp(const struct device *dev, bool enable,
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bool permanent)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint8_t current_level, target_level;
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current_level =
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(regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
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target_level = current_level;
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/*
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* 0xAA = RDP level 0 (no protection)
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* 0xCC = RDP level 2 (permanent protection)
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* others = RDP level 1 (protection active)
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*/
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switch (current_level) {
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case FLASH_STM32_RDP2:
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if (!enable || !permanent) {
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LOG_ERR("RDP level 2 is permanent and can't be changed!");
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return -ENOTSUP;
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}
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break;
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case FLASH_STM32_RDP0:
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if (enable) {
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target_level = FLASH_STM32_RDP1;
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if (permanent) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
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target_level = FLASH_STM32_RDP2;
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#else
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LOG_ERR("Permanent readout protection (RDP "
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"level 0 -> 2) not allowed");
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return -ENOTSUP;
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#endif
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}
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}
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break;
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default: /* FLASH_STM32_RDP1 */
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if (enable && permanent) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
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target_level = FLASH_STM32_RDP2;
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#else
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LOG_ERR("Permanent readout protection (RDP "
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"level 1 -> 2) not allowed");
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return -ENOTSUP;
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#endif
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}
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if (!enable) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW)
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target_level = FLASH_STM32_RDP0;
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#else
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LOG_ERR("Disabling readout protection (RDP "
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"level 1 -> 0) not allowed");
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return -EACCES;
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#endif
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}
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}
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/* Update RDP level if needed */
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if (current_level != target_level) {
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LOG_INF("RDP changed from 0x%02x to 0x%02x", current_level,
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target_level);
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write_optb(dev, FLASH_OPTR_RDP_Msk,
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(uint32_t)target_level << FLASH_OPTR_RDP_Pos);
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}
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return 0;
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}
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int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
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bool *permanent)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint8_t current_level;
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current_level =
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(regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
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/*
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* 0xAA = RDP level 0 (no protection)
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* 0xCC = RDP level 2 (permanent protection)
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* others = RDP level 1 (protection active)
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*/
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switch (current_level) {
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case FLASH_STM32_RDP2:
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*enabled = true;
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*permanent = true;
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break;
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case FLASH_STM32_RDP0:
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*enabled = false;
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*permanent = false;
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break;
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default: /* FLASH_STM32_RDP1 */
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*enabled = true;
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*permanent = false;
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}
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return 0;
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}
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#endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
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void flash_stm32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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static struct flash_pages_layout stm32l4_flash_layout = {
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.pages_count = 0,
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.pages_size = 0,
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};
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ARG_UNUSED(dev);
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if (stm32l4_flash_layout.pages_count == 0) {
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stm32l4_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
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stm32l4_flash_layout.pages_size = FLASH_PAGE_SIZE;
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}
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*layout = &stm32l4_flash_layout;
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*layout_size = 1;
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}
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