7795558ad5
For the flash driver, the base address is the MCU internal flash address (usually 0x8000000). This PR gets the that address from the device tree node "st,stm32-nv-flash" instead of relying on the CONFIG_FLASH_BASE_ADDRESS which might differ when building for another flash memory. Signed-off-by: Francois Ramu <francois.ramu@st.com>
241 lines
6.3 KiB
C
241 lines
6.3 KiB
C
/*
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* Copyright (c) 2018 Aurelien Jarno
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* Copyright (c) 2018 Yong Jin
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <string.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/barrier.h>
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#include <soc.h>
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#include "flash_stm32.h"
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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ARG_UNUSED(write);
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return flash_stm32_range_exists(dev, offset, len);
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_ARTEN) {
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regs->ACR &= ~FLASH_ACR_ARTEN;
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/* Reference manual:
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* The ART cache can be flushed only if the ART accelerator
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* is disabled (ARTEN = 0).
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*/
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regs->ACR |= FLASH_ACR_ARTRST;
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regs->ACR &= ~FLASH_ACR_ARTRST;
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regs->ACR |= FLASH_ACR_ARTEN;
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}
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}
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static int write_byte(const struct device *dev, off_t offset, uint8_t val)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* prepare to write a single byte */
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regs->CR = (regs->CR & CR_PSIZE_MASK) |
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FLASH_PSIZE_BYTE | FLASH_CR_PG;
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/* flush the register write */
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barrier_dsync_fence_full();
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/* write the data */
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*((uint8_t *) offset + FLASH_STM32_BASE_ADDRESS) = val;
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/* flush the register write */
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barrier_dsync_fence_full();
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_sector(const struct device *dev, uint32_t sector)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Dual bank mode, SNB MSB selects the bank2,
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* others select sector, so we remap sector number.
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*/
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#if defined(FLASH_OPTCR_nDBANK) && FLASH_SECTOR_TOTAL == 24
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#if CONFIG_FLASH_SIZE == 2048
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if (sector > 11) {
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sector += 4U;
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}
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#elif CONFIG_FLASH_SIZE == 1024
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if (sector > 7) {
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sector += 8U;
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}
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#endif /* CONFIG_FLASH_SIZE */
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#endif /* defined(FLASH_OPTCR_nDBANK) && FLASH_SECTOR_TOTAL == 24 */
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regs->CR = (regs->CR & ~(FLASH_CR_PSIZE | FLASH_CR_SNB)) |
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FLASH_PSIZE_BYTE |
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FLASH_CR_SER |
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(sector << FLASH_CR_SNB_Pos) |
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FLASH_CR_STRT;
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/* flush the register write */
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barrier_dsync_fence_full();
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
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return rc;
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}
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len)
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{
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struct flash_pages_info info;
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uint32_t start_sector, end_sector;
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uint32_t i;
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int rc = 0;
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rc = flash_get_page_info_by_offs(dev, offset, &info);
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if (rc) {
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return rc;
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}
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start_sector = info.index;
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rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);
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if (rc) {
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return rc;
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}
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end_sector = info.index;
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for (i = start_sector; i <= end_sector; i++) {
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rc = erase_sector(dev, i);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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for (i = 0; i < len; i++, offset++) {
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rc = write_byte(dev, offset, ((const uint8_t *) data)[i]);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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/* Some SoC can run in single or dual bank mode, others can't.
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* Different SoC flash layouts are specified in various reference
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* manuals, but the flash layout for a given number of sectors is
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* consistent across these manuals. The number of sectors is given
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* by the HAL as FLASH_SECTOR_TOTAL. And some SoC that with same
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* FLASH_SECTOR_TOTAL have different flash size.
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*
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* In case of 8 sectors and 24 sectors we need to differentiate
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* between two cases by using the memory size.
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* In case of 24 sectors we need to check if the SoC is running
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* in single or dual bank mode.
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*/
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#ifndef FLASH_SECTOR_TOTAL
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#error "Unknown flash layout"
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#elif FLASH_SECTOR_TOTAL == 2
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static const struct flash_pages_layout stm32f7_flash_layout[] = {
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/* RM0385, table 4: STM32F750xx */
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{.pages_count = 2, .pages_size = KB(32)},
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};
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#elif FLASH_SECTOR_TOTAL == 4
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static const struct flash_pages_layout stm32f7_flash_layout[] = {
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/* RM0431, table 4: STM32F730xx */
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{.pages_count = 4, .pages_size = KB(16)},
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};
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#elif FLASH_SECTOR_TOTAL == 8
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#if CONFIG_FLASH_SIZE == 512
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static const struct flash_pages_layout stm32f7_flash_layout[] = {
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/* RM0431, table 3: STM32F72xxx and STM32F732xx/F733xx */
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 3, .pages_size = KB(128)},
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};
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#elif CONFIG_FLASH_SIZE == 1024
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static const struct flash_pages_layout stm32f7_flash_layout[] = {
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/* RM0385, table 3: STM32F756xx and STM32F74xxx */
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{.pages_count = 4, .pages_size = KB(32)},
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{.pages_count = 1, .pages_size = KB(128)},
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{.pages_count = 3, .pages_size = KB(256)},
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};
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#endif /* CONFIG_FLASH_SIZE */
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#elif FLASH_SECTOR_TOTAL == 24
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static const struct flash_pages_layout stm32f7_flash_layout_single_bank[] = {
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/* RM0410, table 3: STM32F76xxx and STM32F77xxx in single bank */
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{.pages_count = 4, .pages_size = KB(32)},
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{.pages_count = 1, .pages_size = KB(128)},
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{.pages_count = 7, .pages_size = KB(256)},
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};
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static const struct flash_pages_layout stm32f7_flash_layout_dual_bank[] = {
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/* RM0410, table 4: STM32F76xxx and STM32F77xxx in dual bank */
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 7, .pages_size = KB(128)},
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 7, .pages_size = KB(128)},
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};
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#else
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#error "Unknown flash layout"
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#endif/* !defined(FLASH_SECTOR_TOTAL) */
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void flash_stm32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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#if FLASH_OPTCR_nDBANK
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if (FLASH_STM32_REGS(dev)->OPTCR & FLASH_OPTCR_nDBANK) {
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*layout = stm32f7_flash_layout_single_bank;
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*layout_size = ARRAY_SIZE(stm32f7_flash_layout_single_bank);
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} else {
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*layout = stm32f7_flash_layout_dual_bank;
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*layout_size = ARRAY_SIZE(stm32f7_flash_layout_dual_bank);
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}
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#else
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ARG_UNUSED(dev);
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*layout = stm32f7_flash_layout;
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*layout_size = ARRAY_SIZE(stm32f7_flash_layout);
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#endif
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}
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