7795558ad5
For the flash driver, the base address is the MCU internal flash address (usually 0x8000000). This PR gets the that address from the device tree node "st,stm32-nv-flash" instead of relying on the CONFIG_FLASH_BASE_ADDRESS which might differ when building for another flash memory. Signed-off-by: Francois Ramu <francois.ramu@st.com>
480 lines
12 KiB
C
480 lines
12 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2023 Google Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/barrier.h>
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#include <soc.h>
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#include "flash_stm32.h"
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LOG_MODULE_REGISTER(flash_stm32f4x, CONFIG_FLASH_LOG_LEVEL);
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#if FLASH_STM32_WRITE_BLOCK_SIZE == 8
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typedef uint64_t flash_prg_t;
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#define FLASH_PROGRAM_SIZE FLASH_PSIZE_DOUBLE_WORD
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#elif FLASH_STM32_WRITE_BLOCK_SIZE == 4
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typedef uint32_t flash_prg_t;
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#define FLASH_PROGRAM_SIZE FLASH_PSIZE_WORD
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#elif FLASH_STM32_WRITE_BLOCK_SIZE == 2
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typedef uint16_t flash_prg_t;
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#define FLASH_PROGRAM_SIZE FLASH_PSIZE_HALF_WORD
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#elif FLASH_STM32_WRITE_BLOCK_SIZE == 1
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typedef uint8_t flash_prg_t;
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#define FLASH_PROGRAM_SIZE FLASH_PSIZE_BYTE
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#else
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#error Write block size must be a power of 2, from 1 to 8
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#endif
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len,
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bool write)
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{
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ARG_UNUSED(write);
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#if (FLASH_SECTOR_TOTAL == 12) && defined(FLASH_OPTCR_DB1M)
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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/*
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* RM0090, table 7.1: STM32F42xxx, STM32F43xxx
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*/
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if (regs->OPTCR & FLASH_OPTCR_DB1M) {
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/* Device configured in Dual Bank, but not supported for now */
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return false;
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}
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#endif
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return flash_stm32_range_exists(dev, offset, len);
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}
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static inline void flush_cache(FLASH_TypeDef *regs)
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{
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if (regs->ACR & FLASH_ACR_DCEN) {
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regs->ACR &= ~FLASH_ACR_DCEN;
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/* Datasheet: DCRST: Data cache reset
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* This bit can be written only when the data cache is disabled
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*/
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= ~FLASH_ACR_DCRST;
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regs->ACR |= FLASH_ACR_DCEN;
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}
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if (regs->ACR & FLASH_ACR_ICEN) {
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regs->ACR &= ~FLASH_ACR_ICEN;
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/* Datasheet: ICRST: Instruction cache reset :
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* This bit can be written only when the instruction cache
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* is disabled
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*/
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regs->ACR |= FLASH_ACR_ICRST;
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regs->ACR &= ~FLASH_ACR_ICRST;
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regs->ACR |= FLASH_ACR_ICEN;
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}
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}
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static int write_value(const struct device *dev, off_t offset, flash_prg_t val)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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#if defined(FLASH_OPTCR_DB1M)
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bool dcache_enabled = false;
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#endif /* FLASH_OPTCR_DB*/
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uint32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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#if defined(FLASH_OPTCR_DB1M)
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/*
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* Disable the data cache to avoid the silicon errata ES0206 Rev 16 2.2.12:
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* "Data cache might be corrupted during Flash memory read-while-write operation"
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*/
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if (regs->ACR & FLASH_ACR_DCEN) {
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dcache_enabled = true;
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regs->ACR &= (~FLASH_ACR_DCEN);
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}
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#endif /* FLASH_OPTCR_DB1M */
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regs->CR &= CR_PSIZE_MASK;
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regs->CR |= FLASH_PROGRAM_SIZE;
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regs->CR |= FLASH_CR_PG;
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/* flush the register write */
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tmp = regs->CR;
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*((flash_prg_t *)(offset + FLASH_STM32_BASE_ADDRESS)) = val;
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= (~FLASH_CR_PG);
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#if defined(FLASH_OPTCR_DB1M)
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/* Reset/enable the data cache if previously enabled */
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if (dcache_enabled) {
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regs->ACR |= FLASH_ACR_DCRST;
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regs->ACR &= (~FLASH_ACR_DCRST);
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regs->ACR |= FLASH_ACR_DCEN;
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}
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#endif /* FLASH_OPTCR_DB1M */
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return rc;
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}
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static int erase_sector(const struct device *dev, uint32_t sector)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->CR & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/*
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* If an erase operation in Flash memory also concerns data
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* in the instruction cache, the user has to ensure that these data
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* are rewritten before they are accessed during code execution.
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*/
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flush_cache(regs);
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#if FLASH_SECTOR_TOTAL == 24
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/*
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* RM0090, §3.9.8: STM32F42xxx, STM32F43xxx
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* RM0386, §3.7.5: STM32F469xx, STM32F479xx
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*/
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if (sector >= 12) {
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/* From sector 12, SNB is offset by 0b10000 */
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sector += 4U;
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}
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#endif
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regs->CR &= CR_PSIZE_MASK;
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regs->CR |= FLASH_PROGRAM_SIZE;
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regs->CR &= ~FLASH_CR_SNB;
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regs->CR |= FLASH_CR_SER | (sector << 3);
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regs->CR |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->CR;
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rc = flash_stm32_wait_flash_idle(dev);
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regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
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return rc;
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}
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len)
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{
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struct flash_pages_info info;
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uint32_t start_sector, end_sector;
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uint32_t i;
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int rc = 0;
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rc = flash_get_page_info_by_offs(dev, offset, &info);
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if (rc) {
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return rc;
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}
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start_sector = info.index;
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rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);
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if (rc) {
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return rc;
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}
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end_sector = info.index;
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for (i = start_sector; i <= end_sector; i++) {
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rc = erase_sector(dev, i);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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flash_prg_t value;
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for (i = 0; i < len / sizeof(flash_prg_t); i++) {
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value = UNALIGNED_GET((flash_prg_t *)data + i);
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rc = write_value(dev, offset + i * sizeof(flash_prg_t), value);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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static __unused int write_optb(const struct device *dev, uint32_t mask,
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uint32_t value)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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int rc;
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if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
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return -EIO;
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}
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if ((regs->OPTCR & mask) == value) {
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return 0;
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}
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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regs->OPTCR = (regs->OPTCR & ~mask) | value;
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regs->OPTCR |= FLASH_OPTCR_OPTSTRT;
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/* Make sure previous write is completed. */
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barrier_dsync_fence_full();
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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return 0;
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}
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#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
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int flash_stm32_update_wp_sectors(const struct device *dev,
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uint32_t changed_sectors,
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uint32_t protected_sectors)
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{
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changed_sectors <<= FLASH_OPTCR_nWRP_Pos;
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protected_sectors <<= FLASH_OPTCR_nWRP_Pos;
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if ((changed_sectors & FLASH_OPTCR_nWRP_Msk) != changed_sectors) {
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return -EINVAL;
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}
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/* Sector is protected when bit == 0. Flip protected_sectors bits */
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protected_sectors = ~protected_sectors & changed_sectors;
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return write_optb(dev, changed_sectors, protected_sectors);
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}
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int flash_stm32_get_wp_sectors(const struct device *dev,
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uint32_t *protected_sectors)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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*protected_sectors =
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(~regs->OPTCR & FLASH_OPTCR_nWRP_Msk) >> FLASH_OPTCR_nWRP_Pos;
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return 0;
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}
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#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
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int flash_stm32_update_rdp(const struct device *dev, bool enable,
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bool permanent)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint8_t current_level, target_level;
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current_level =
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(regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;
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target_level = current_level;
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/*
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* 0xAA = RDP level 0 (no protection)
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* 0xCC = RDP level 2 (permanent protection)
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* others = RDP level 1 (protection active)
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*/
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switch (current_level) {
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case FLASH_STM32_RDP2:
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if (!enable || !permanent) {
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LOG_ERR("RDP level 2 is permanent and can't be changed!");
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return -ENOTSUP;
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}
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break;
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case FLASH_STM32_RDP0:
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if (enable) {
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target_level = FLASH_STM32_RDP1;
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if (permanent) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
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target_level = FLASH_STM32_RDP2;
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#else
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LOG_ERR("Permanent readout protection (RDP "
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"level 0 -> 2) not allowed");
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return -ENOTSUP;
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#endif
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}
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}
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break;
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default: /* FLASH_STM32_RDP1 */
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if (enable && permanent) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_PERMANENT_ALLOW)
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target_level = FLASH_STM32_RDP2;
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#else
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LOG_ERR("Permanent readout protection (RDP "
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"level 1 -> 2) not allowed");
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return -ENOTSUP;
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#endif
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}
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if (!enable) {
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION_DISABLE_ALLOW)
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target_level = FLASH_STM32_RDP0;
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#else
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LOG_ERR("Disabling readout protection (RDP "
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"level 1 -> 0) not allowed");
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return -EACCES;
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#endif
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}
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}
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/* Update RDP level if needed */
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if (current_level != target_level) {
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LOG_INF("RDP changed from 0x%02x to 0x%02x", current_level,
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target_level);
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write_optb(dev, FLASH_OPTCR_RDP_Msk,
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(uint32_t)target_level << FLASH_OPTCR_RDP_Pos);
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}
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return 0;
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}
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int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
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bool *permanent)
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{
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FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
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uint8_t current_level;
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current_level =
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(regs->OPTCR & FLASH_OPTCR_RDP_Msk) >> FLASH_OPTCR_RDP_Pos;
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/*
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* 0xAA = RDP level 0 (no protection)
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* 0xCC = RDP level 2 (permanent protection)
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* others = RDP level 1 (protection active)
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*/
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switch (current_level) {
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case FLASH_STM32_RDP2:
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*enabled = true;
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*permanent = true;
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break;
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case FLASH_STM32_RDP0:
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*enabled = false;
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*permanent = false;
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break;
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default: /* FLASH_STM32_RDP1 */
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*enabled = true;
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*permanent = false;
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}
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return 0;
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}
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#endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
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/*
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* Different SoC flash layouts are specified in across various
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* reference manuals, but the flash layout for a given number of
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* sectors is consistent across these manuals, with one "gotcha". The
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* number of sectors is given by the HAL as FLASH_SECTOR_TOTAL.
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*
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* The only "gotcha" is that when there are 24 sectors, they are split
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* across 2 "banks" of 12 sectors each, with another set of small
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* sectors (16 KB) in the second bank occurring after the large ones
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* (128 KB) in the first. We could consider supporting this as two
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* devices to make the layout cleaner, but this will do for now.
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*/
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#ifndef FLASH_SECTOR_TOTAL
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#error "Unknown flash layout"
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#else /* defined(FLASH_SECTOR_TOTAL) */
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#if FLASH_SECTOR_TOTAL == 5
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/* RM0401, table 5: STM32F410Tx, STM32F410Cx, STM32F410Rx */
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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};
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#elif FLASH_SECTOR_TOTAL == 6
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/* RM0368, table 5: STM32F401xC */
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 1, .pages_size = KB(128)},
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};
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#elif FLASH_SECTOR_TOTAL == 8
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/*
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* RM0368, table 5: STM32F401xE
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* RM0383, table 4: STM32F411xE
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* RM0390, table 4: STM32F446xx
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*/
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 3, .pages_size = KB(128)},
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};
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#elif FLASH_SECTOR_TOTAL == 12
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/*
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* RM0090, table 5: STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx
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* RM0402, table 5: STM32F412Zx, STM32F412Vx, STM32F412Rx, STM32F412Cx
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*/
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 7, .pages_size = KB(128)},
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};
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#elif FLASH_SECTOR_TOTAL == 16
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/* RM0430, table 5.: STM32F413xx, STM32F423xx */
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 11, .pages_size = KB(128)},
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};
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#elif FLASH_SECTOR_TOTAL == 24
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static const struct flash_pages_layout stm32f4_flash_layout[] = {
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/*
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* RM0090, table 6: STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx
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* RM0386, table 4: STM32F469xx, STM32F479xx
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*/
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 7, .pages_size = KB(128)},
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{.pages_count = 4, .pages_size = KB(16)},
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{.pages_count = 1, .pages_size = KB(64)},
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{.pages_count = 7, .pages_size = KB(128)},
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};
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#else
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#error "Unknown flash layout"
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#endif /* FLASH_SECTOR_TOTAL == 5 */
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#endif/* !defined(FLASH_SECTOR_TOTAL) */
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void flash_stm32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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ARG_UNUSED(dev);
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*layout = stm32f4_flash_layout;
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*layout_size = ARRAY_SIZE(stm32f4_flash_layout);
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}
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