7795558ad5
For the flash driver, the base address is the MCU internal flash address (usually 0x8000000). This PR gets the that address from the device tree node "st,stm32-nv-flash" instead of relying on the CONFIG_FLASH_BASE_ADDRESS which might differ when building for another flash memory. Signed-off-by: Francois Ramu <francois.ramu@st.com>
322 lines
10 KiB
C
322 lines
10 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS.
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* Copyright (c) 2023 Google Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
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#define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
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#include <zephyr/drivers/flash.h>
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#endif
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/* Get the base address of the flash from the DTS node */
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#define FLASH_STM32_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash))
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struct flash_stm32_priv {
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FLASH_TypeDef *regs;
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#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
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DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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#endif
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struct k_sem sem;
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};
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#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#define FLASH_STM32_WRITE_BLOCK_SIZE \
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DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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/* as flash node property 'write-block-size' */
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32H5X)
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/* FLASH register names differ for this serie */
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#define FLASH_NSSR_BSY FLASH_SR_BSY
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#define OPTR OPTCR
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#endif /* CONFIG_SOC_SERIES_STM32H5X */
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/* Differentiate between arm trust-zone non-secure/secure, and others. */
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#if defined(FLASH_NSSR_NSBSY) || defined(FLASH_NSSR_BSY) /* For mcu w. TZ in non-secure mode */
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#define FLASH_SECURITY_NS
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#define FLASH_STM32_SR NSSR
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#elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */
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#error Flash is not supported in secure mode
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#define FLASH_SECURITY_SEC
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#else
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#define FLASH_SECURITY_NA /* For series which does not have
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* secured or non-secured mode
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*/
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#define FLASH_STM32_SR SR
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#endif
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#define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
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#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
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/* Redefinitions of flags and masks to harmonize stm32 series: */
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#if defined(CONFIG_SOC_SERIES_STM32U5X)
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#define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
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#define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
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#define FLASH_STM32_NSPG FLASH_NSCR_PG
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#define FLASH_STM32_NSBKER_MSK FLASH_NSCR_BKER_Msk
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#define FLASH_STM32_NSBKER FLASH_NSCR_BKER
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#define FLASH_STM32_NSPER FLASH_NSCR_PER
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#define FLASH_STM32_NSPNB_MSK FLASH_NSCR_PNB_Msk
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#define FLASH_STM32_NSPNB_POS FLASH_NSCR_PNB_Pos
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#define FLASH_STM32_NSPNB FLASH_NSCR_PNB
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#define FLASH_STM32_NSSTRT FLASH_NSCR_STRT
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#define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
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#elif defined(CONFIG_SOC_SERIES_STM32H5X)
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#define FLASH_OPTR_SWAP_BANK FLASH_OPTCR_SWAP_BANK
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#define FLASH_STM32_NSLOCK FLASH_CR_LOCK
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#define FLASH_STM32_DBANK 1
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#define FLASH_STM32_NSPG FLASH_CR_PG
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#define FLASH_STM32_NSBKER_MSK FLASH_CR_BKSEL_Msk
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#define FLASH_STM32_NSBKER FLASH_CR_BKSEL
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#define FLASH_STM32_NSPER FLASH_CR_SER
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#define FLASH_STM32_NSPNB_MSK FLASH_CR_SNB_Msk
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#define FLASH_STM32_NSPNB_POS FLASH_CR_SNB_Pos
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#define FLASH_STM32_NSPNB FLASH_CR_PNB
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#define FLASH_STM32_NSSTRT FLASH_CR_START
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/* TODO: get values from the cmsis and stm32h5_hal_flash.h */
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#undef FLASH_SIZE
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/* Retrieve the FLASH SIZE from the DTS instead of cmsis as it seems erroneous */
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#define FLASH_SIZE (CONFIG_FLASH_SIZE * 1024)
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/* Values are redefined below from the stm32h5_hal_flash.h */
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#define FLASH_PAGE_SIZE (FLASH_SECTOR_SIZE)
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#define FLASH_PAGE_NB (FLASH_SECTOR_NB)
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#define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
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#define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
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#elif defined(CONFIG_SOC_SERIES_STM32L5X)
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#define FLASH_STM32_NSLOCK FLASH_NSCR_NSLOCK
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#define FLASH_STM32_NSPG FLASH_NSCR_NSPG
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#define FLASH_STM32_NSBKER_MSK FLASH_NSCR_NSBKER_Pos
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#define FLASH_STM32_NSBKER FLASH_NSCR_NSBKER
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#define FLASH_STM32_NSPER FLASH_NSCR_NSPER
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#define FLASH_STM32_NSPNB_MSK FLASH_NSCR_NSPNB_Msk
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#define FLASH_STM32_NSPNB_POS FLASH_NSCR_NSPNB_Pos
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#define FLASH_STM32_NSPNB FLASH_NSCR_NSPNB
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#define FLASH_STM32_NSSTRT FLASH_NSCR_NSSTRT
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#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
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#define NSCR NSCR1
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#define FLASH_STM32_NSLOCK FLASH_NSCR1_LOCK
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#define FLASH_STM32_NSPG FLASH_NSCR1_PG
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#define FLASH_STM32_NSBKER_MSK FLASH_NSCR1_BKER_Msk
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#define FLASH_STM32_NSBKER FLASH_NSCR1_BKER
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#define FLASH_STM32_NSPER FLASH_NSCR1_PER
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#define FLASH_STM32_NSPNB_MSK FLASH_NSCR1_PNB_Msk
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#define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
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#define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
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#define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
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#endif /* CONFIG_SOC_SERIES_STM32U5X */
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#if defined(FLASH_OPTR_DBANK)
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#define FLASH_STM32_DBANK FLASH_OPTR_DBANK
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#endif /* FLASH_OPTR_DBANK */
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#if defined(CONFIG_SOC_SERIES_STM32G0X)
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#if defined(FLASH_FLAG_BSY2)
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#define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
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#else
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#define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1)
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#endif /* defined(FLASH_FLAG_BSY2) */
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#else
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#define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY)
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32G0X)
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#define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY)
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#elif defined(FLASH_FLAG_CFGBSY)
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#define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY)
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32G0X)
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/* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
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#define FLASH_STM32_SR_OPERR FLASH_SR_OPERR
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#define FLASH_STM32_SR_PGERR 0
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#define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR
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#define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR
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#define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR
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#define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR
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#define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR
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#define FLASH_STM32_SR_MISERR FLASH_SR_MISERR
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#define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR
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#if defined(FLASH_SR_RDERR)
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#define FLASH_STM32_SR_RDERR FLASH_SR_RDERR
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#else
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#define FLASH_STM32_SR_RDERR 0
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#endif
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#define FLASH_STM32_SR_PGPERR 0
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#else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
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#if defined(FLASH_FLAG_OPERR)
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#define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR
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#else
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#define FLASH_STM32_SR_OPERR 0
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#endif
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#if defined(FLASH_FLAG_PGERR)
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#define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR
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#else
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#define FLASH_STM32_SR_PGERR 0
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#endif
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#if defined(FLASH_FLAG_PROGERR)
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#define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR
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#else
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#define FLASH_STM32_SR_PROGERR 0
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#endif
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#if defined(FLASH_FLAG_WRPERR)
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#define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR
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#else
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#define FLASH_STM32_SR_WRPERR 0
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#endif
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#if defined(FLASH_FLAG_PGAERR)
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#define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR
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#else
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#define FLASH_STM32_SR_PGAERR 0
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#endif
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#if defined(FLASH_FLAG_SIZERR)
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#define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR
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#else
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#define FLASH_STM32_SR_SIZERR 0
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#endif
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#if defined(FLASH_FLAG_PGSERR)
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#define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR
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#else
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#define FLASH_STM32_SR_PGSERR 0
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#endif
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#if defined(FLASH_FLAG_MISERR)
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#define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR
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#else
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#define FLASH_STM32_SR_MISERR 0
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#endif
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#if defined(FLASH_FLAG_FASTERR)
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#define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR
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#else
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#define FLASH_STM32_SR_FASTERR 0
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#endif
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#if defined(FLASH_FLAG_RDERR)
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#define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR
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#else
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#define FLASH_STM32_SR_RDERR 0
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#endif
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#if defined(FLASH_FLAG_PGPERR)
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#define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR
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#else
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#define FLASH_STM32_SR_PGPERR 0
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#endif
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#endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
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#define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \
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FLASH_STM32_SR_PGERR | \
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FLASH_STM32_SR_PROGERR | \
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FLASH_STM32_SR_WRPERR | \
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FLASH_STM32_SR_PGAERR | \
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FLASH_STM32_SR_SIZERR | \
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FLASH_STM32_SR_PGSERR | \
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FLASH_STM32_SR_MISERR | \
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FLASH_STM32_SR_FASTERR | \
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FLASH_STM32_SR_RDERR | \
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FLASH_STM32_SR_PGPERR)
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#define FLASH_STM32_RDP0 0xAA
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#define FLASH_STM32_RDP2 0xCC
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#define FLASH_STM32_RDP1 \
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DT_PROP(DT_INST(0, st_stm32_flash_controller), st_rdp1_enable_byte)
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#if FLASH_STM32_RDP1 == FLASH_STM32_RDP0 || FLASH_STM32_RDP1 == FLASH_STM32_RDP2
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#error RDP1 byte has to be different than RDP0 and RDP2 byte
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#endif
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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static inline bool flash_stm32_range_exists(const struct device *dev,
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off_t offset,
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uint32_t len)
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{
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struct flash_pages_info info;
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return !(flash_get_page_info_by_offs(dev, offset, &info) ||
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flash_get_page_info_by_offs(dev, offset + len - 1, &info));
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static inline bool flash_stm32_valid_write(off_t offset, uint32_t len)
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{
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return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) &&
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(len % FLASH_STM32_WRITE_BLOCK_SIZE == 0U));
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}
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bool flash_stm32_valid_range(const struct device *dev, off_t offset,
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uint32_t len, bool write);
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int flash_stm32_write_range(const struct device *dev, unsigned int offset,
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const void *data, unsigned int len);
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int flash_stm32_block_erase_loop(const struct device *dev,
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unsigned int offset,
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unsigned int len);
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int flash_stm32_wait_flash_idle(const struct device *dev);
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int flash_stm32_option_bytes_lock(const struct device *dev, bool enable);
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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int flash_stm32_check_status(const struct device *dev);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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void flash_stm32_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size);
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#endif
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#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
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int flash_stm32_update_wp_sectors(const struct device *dev,
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uint32_t changed_sectors,
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uint32_t protected_sectors);
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int flash_stm32_get_wp_sectors(const struct device *dev,
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uint32_t *protected_sectors);
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#endif
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
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int flash_stm32_update_rdp(const struct device *dev, bool enable,
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bool permanent);
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int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
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bool *permanent);
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#endif
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/* Flash extended operations */
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#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
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int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in,
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void *out);
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#endif
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#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
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int flash_stm32_ex_op_rdp(const struct device *dev, const uintptr_t in,
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void *out);
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#endif
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#endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
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