b0ce525b90
Change device tree VW routing to a form allowing overrides. Add two new DT optional properties for specifying the reset source and reset value of each virtual wire. Only virtual wires that are enabled using the status property are modified. NOTE: eSPI virtual wires are controlled in groups of 4 by hardware. The optional reset signal source properties applies to all four virtual wires in the group. If this field is changed from the hardware default, it should be changed for only one virtual wire in the group. If the property exists in more than one wire in the group it must be set to the same value. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
120 lines
2.3 KiB
C
120 lines
2.3 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_
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#define ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/espi.h>
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#include <zephyr/drivers/pinctrl.h>
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/* #define ESPI_XEC_V2_DEBUG 1 */
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struct espi_isr {
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uint8_t girq_id;
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uint8_t girq_pos;
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void (*the_isr)(const struct device *dev);
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};
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struct espi_vw_isr {
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uint8_t signal;
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uint8_t girq_id;
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uint8_t girq_pos;
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void (*the_isr)(int girq, int bpos, void *dev);
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};
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struct espi_xec_irq_info {
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uint8_t gid; /* GIRQ id [8, 26] */
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uint8_t gpos; /* bit position in GIRQ [0, 31] */
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uint8_t anid; /* Aggregated GIRQ NVIC number */
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uint8_t dnid; /* Direct GIRQ NVIC number */
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};
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struct espi_xec_config {
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uint32_t base_addr;
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uint32_t vw_base_addr;
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uint8_t pcr_idx;
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uint8_t pcr_bitpos;
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uint8_t irq_info_size;
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uint8_t rsvd[1];
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const struct espi_xec_irq_info *irq_info_list;
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const struct pinctrl_dev_config *pcfg;
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};
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#define ESPI_XEC_CONFIG(dev) \
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((struct espi_xec_config * const)(dev)->config)
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struct espi_xec_data {
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sys_slist_t callbacks;
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struct k_sem tx_lock;
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struct k_sem rx_lock;
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struct k_sem flash_lock;
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#ifdef ESPI_XEC_V2_DEBUG
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uint32_t espi_rst_count;
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#endif
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};
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#define ESPI_XEC_DATA(dev) \
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((struct espi_xec_data * const)(dev)->data)
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struct xec_signal {
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uint8_t host_idx;
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uint8_t bit;
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uint8_t xec_reg_idx;
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uint8_t flags;
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};
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enum mchp_msvw_regs {
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MCHP_MSVW00,
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MCHP_MSVW01,
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MCHP_MSVW02,
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MCHP_MSVW03,
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MCHP_MSVW04,
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MCHP_MSVW05,
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MCHP_MSVW06,
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MCHP_MSVW07,
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MCHP_MSVW08,
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};
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enum mchp_smvw_regs {
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MCHP_SMVW00,
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MCHP_SMVW01,
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MCHP_SMVW02,
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MCHP_SMVW03,
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MCHP_SMVW04,
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MCHP_SMVW05,
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MCHP_SMVW06,
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MCHP_SMVW07,
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MCHP_SMVW08,
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};
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enum xec_espi_girq_idx {
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pc_girq_idx = 0,
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bm1_girq_idx,
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bm2_girq_idx,
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ltr_girq_idx,
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oob_up_girq_idx,
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oob_dn_girq_idx,
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fc_girq_idx,
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rst_girq_idx,
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vw_ch_en_girq_idx,
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max_girq_idx,
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};
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int xec_host_dev_init(const struct device *dev);
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int xec_host_dev_connect_irqs(const struct device *dev);
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int espi_xec_read_lpc_request(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data);
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int espi_xec_write_lpc_request(const struct device *dev,
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enum lpc_peripheral_opcode op,
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uint32_t *data);
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#endif /* ZEPHYR_DRIVERS_ESPI_MCHP_XEC_ESPI_V2_H_ */
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