5925a4670b
Added intel LPSS DMA interface using dw common to support usage of internal DMA in LPSS UART, SPI and I2C for transfer and receive operations. Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
297 lines
8.2 KiB
C
297 lines
8.2 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_DMA_DMA_DW_COMMON_H_
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#define ZEPHYR_DRIVERS_DMA_DMA_DW_COMMON_H_
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#include <zephyr/sys/atomic.h>
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#include <zephyr/drivers/dma.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MASK(b_hi, b_lo) \
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(((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
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#define SET_BIT(b, x) (((x) & 1) << (b))
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#define SET_BITS(b_hi, b_lo, x) \
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(((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
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#define DW_MAX_CHAN 8
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#define DW_CHAN_COUNT CONFIG_DMA_DW_CHANNEL_COUNT
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#define DW_CH_SIZE 0x58
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#define DW_CHAN_OFFSET(chan) (DW_CH_SIZE * chan)
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#define DW_ADDR_MASK_32 BIT_MASK(32)
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#define DW_ADDR_RIGHT_SHIFT 32
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#define DW_SAR(chan) \
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(0x0000 + DW_CHAN_OFFSET(chan))
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#define DW_DAR(chan) \
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(0x0008 + DW_CHAN_OFFSET(chan))
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#define DW_LLP(chan) \
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(0x0010 + DW_CHAN_OFFSET(chan))
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#define DW_CTRL_LOW(chan) \
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(0x0018 + DW_CHAN_OFFSET(chan))
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#define DW_CTRL_HIGH(chan) \
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(0x001C + DW_CHAN_OFFSET(chan))
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#define DW_CFG_LOW(chan) \
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(0x0040 + DW_CHAN_OFFSET(chan))
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#define DW_CFG_HIGH(chan) \
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(0x0044 + DW_CHAN_OFFSET(chan))
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#define DW_DSR(chan) \
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(0x0050 + DW_CHAN_OFFSET(chan))
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#ifdef CONFIG_DMA_64BIT
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#define DW_SAR_HI(chan) \
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(0x0004 + DW_CHAN_OFFSET(chan))
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#define DW_DAR_HI(chan) \
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(0x000C + DW_CHAN_OFFSET(chan))
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#endif
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/* registers */
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#define DW_RAW_TFR 0x02C0
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#define DW_RAW_BLOCK 0x02C8
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#define DW_RAW_SRC_TRAN 0x02D0
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#define DW_RAW_DST_TRAN 0x02D8
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#define DW_RAW_ERR 0x02E0
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#define DW_STATUS_TFR 0x02E8
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#define DW_STATUS_BLOCK 0x02F0
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#define DW_STATUS_SRC_TRAN 0x02F8
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#define DW_STATUS_DST_TRAN 0x0300
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#define DW_STATUS_ERR 0x0308
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#define DW_MASK_TFR 0x0310
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#define DW_MASK_BLOCK 0x0318
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#define DW_MASK_SRC_TRAN 0x0320
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#define DW_MASK_DST_TRAN 0x0328
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#define DW_MASK_ERR 0x0330
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#define DW_CLEAR_TFR 0x0338
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#define DW_CLEAR_BLOCK 0x0340
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#define DW_CLEAR_SRC_TRAN 0x0348
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#define DW_CLEAR_DST_TRAN 0x0350
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#define DW_CLEAR_ERR 0x0358
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#define DW_INTR_STATUS 0x0360
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#define DW_DMA_CFG 0x0398
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#define DW_DMA_CHAN_EN 0x03A0
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#define DW_FIFO_PART0_LO 0x400
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#define DW_FIFO_PART0_HI 0x404
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#define DW_FIFO_PART1_LO 0x408
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#define DW_FIFO_PART1_HI 0x40C
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/* channel bits */
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#define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
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#define DW_CHAN_WRITE_EN(chan) BIT((chan) + DW_MAX_CHAN)
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#define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
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#define DW_CHAN(chan) BIT(chan)
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#define DW_CHAN_MASK_ALL DW_CHAN_WRITE_EN_ALL
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#define DW_CHAN_MASK(chan) DW_CHAN_WRITE_EN(chan)
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#define DW_CHAN_UNMASK_ALL (DW_CHAN_WRITE_EN_ALL | DW_CHAN_ALL)
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#define DW_CHAN_UNMASK(chan) (DW_CHAN_WRITE_EN(chan) | DW_CHAN(chan))
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/* CFG_LO */
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#define DW_CFGL_RELOAD_DST BIT(31)
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#define DW_CFGL_RELOAD_SRC BIT(30)
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#define DW_CFGL_DRAIN BIT(10) /* For Intel GPDMA variant only */
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#define DW_CFGL_SRC_SW_HS BIT(10) /* For Synopsys variant only */
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#define DW_CFGL_DST_SW_HS BIT(11) /* For Synopsys variant only */
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#define DW_CFGL_FIFO_EMPTY BIT(9)
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#define DW_CFGL_SUSPEND BIT(8)
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#define DW_CFGL_CTL_HI_UPD_EN BIT(5)
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/* CFG_HI */
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#define DW_CFGH_DST_PER_EXT(x) SET_BITS(31, 30, x)
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#define DW_CFGH_SRC_PER_EXT(x) SET_BITS(29, 28, x)
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#define DW_CFGH_DST_PER(x) SET_BITS(7, 4, x)
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#define DW_CFGH_SRC_PER(x) SET_BITS(3, 0, x)
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#define DW_CFGH_DST(x) \
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(DW_CFGH_DST_PER_EXT((x) >> 4) | DW_CFGH_DST_PER(x))
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#define DW_CFGH_SRC(x) \
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(DW_CFGH_SRC_PER_EXT((x) >> 4) | DW_CFGH_SRC_PER(x))
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/* CTL_LO */
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#define DW_CTLL_RELOAD_DST BIT(31)
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#define DW_CTLL_RELOAD_SRC BIT(30)
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#define DW_CTLL_LLP_S_EN BIT(28)
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#define DW_CTLL_LLP_D_EN BIT(27)
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#define DW_CTLL_SMS(x) SET_BIT(25, x)
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#define DW_CTLL_DMS(x) SET_BIT(23, x)
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#define DW_CTLL_FC_P2P SET_BITS(21, 20, 3)
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#define DW_CTLL_FC_P2M SET_BITS(21, 20, 2)
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#define DW_CTLL_FC_M2P SET_BITS(21, 20, 1)
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#define DW_CTLL_FC_M2M SET_BITS(21, 20, 0)
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#define DW_CTLL_D_SCAT_EN BIT(18)
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#define DW_CTLL_S_GATH_EN BIT(17)
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#define DW_CTLL_SRC_MSIZE(x) SET_BITS(16, 14, x)
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#define DW_CTLL_DST_MSIZE(x) SET_BITS(13, 11, x)
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#define DW_CTLL_SRC_FIX SET_BITS(10, 9, 2)
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#define DW_CTLL_SRC_DEC SET_BITS(10, 9, 1)
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#define DW_CTLL_SRC_INC SET_BITS(10, 9, 0)
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#define DW_CTLL_DST_FIX SET_BITS(8, 7, 2)
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#define DW_CTLL_DST_DEC SET_BITS(8, 7, 1)
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#define DW_CTLL_DST_INC SET_BITS(8, 7, 0)
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#define DW_CTLL_SRC_WIDTH(x) SET_BITS(6, 4, x)
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#define DW_CTLL_DST_WIDTH(x) SET_BITS(3, 1, x)
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#define DW_CTLL_INT_EN BIT(0)
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#define DW_CTLL_SRC_WIDTH_MASK MASK(6, 4)
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#define DW_CTLL_SRC_WIDTH_SHIFT 4
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#define DW_CTLL_DST_WIDTH_MASK MASK(3, 1)
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#define DW_CTLL_DST_WIDTH_SHIFT 1
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/* CTL_HI */
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#define DW_CTLH_CLASS(x) SET_BITS(31, 29, x)
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#define DW_CTLH_WEIGHT(x) SET_BITS(28, 18, x)
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#define DW_CTLH_DONE(x) SET_BIT(17, x)
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#define DW_CTLH_BLOCK_TS_MASK MASK(16, 0)
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/* DSR */
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#define DW_DSR_DSC(x) SET_BITS(31, 20, x)
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#define DW_DSR_DSI(x) SET_BITS(19, 0, x)
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/* FIFO_PART */
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#define DW_FIFO_SIZE 0x80
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#define DW_FIFO_UPD BIT(26)
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#define DW_FIFO_CHx(x) SET_BITS(25, 13, x)
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#define DW_FIFO_CHy(x) SET_BITS(12, 0, x)
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/* number of tries to wait for reset */
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#define DW_DMA_CFG_TRIES 10000
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/* channel drain timeout in microseconds */
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#define DW_DMA_TIMEOUT 1333
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/* min number of elems for config with irq disabled */
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#define DW_DMA_CFG_NO_IRQ_MIN_ELEMS 3
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#define DW_DMA_CHANNEL_REGISTER_OFFSET_END 0x50
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#define DW_DMA_IP_REGISTER_OFFSET_END 0x418
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#define DW_DMA_IP_REGISTER_OFFSET_START 0x2C0
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/* linked list item address */
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#define DW_DMA_LLI_ADDRESS(lli, dir) \
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(((dir) == MEMORY_TO_PERIPHERAL) ? ((lli)->sar) : ((lli)->dar))
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/* TODO: add FIFO sizes */
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struct dw_chan_arbit_data {
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uint16_t class;
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uint16_t weight;
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};
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struct dw_drv_plat_data {
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struct dw_chan_arbit_data chan[DW_CHAN_COUNT];
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};
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/* DMA descriptor used by HW */
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struct dw_lli {
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#ifdef CONFIG_DMA_64BIT
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uint64_t sar;
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uint64_t dar;
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#else
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uint32_t sar;
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uint32_t dar;
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#endif
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uint32_t llp;
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uint32_t ctrl_lo;
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uint32_t ctrl_hi;
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uint32_t sstat;
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uint32_t dstat;
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/* align to 32 bytes to not cross cache line
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* in case of more than two items
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*/
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uint32_t reserved;
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} __packed;
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/* pointer data for DW DMA buffer */
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struct dw_dma_ptr_data {
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uint32_t current_ptr;
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uint32_t start_ptr;
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uint32_t end_ptr;
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uint32_t hw_ptr;
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uint32_t buffer_bytes;
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};
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/* State tracking for each channel */
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enum dw_dma_state {
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DW_DMA_IDLE,
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DW_DMA_PREPARED,
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DW_DMA_SUSPENDED,
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DW_DMA_ACTIVE,
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};
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/* data for each DMA channel */
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struct dw_dma_chan_data {
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uint32_t direction;
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enum dw_dma_state state;
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struct dw_lli *lli; /* allocated array of LLI's */
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uint32_t lli_count; /* number of lli's in the allocation */
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struct dw_lli *lli_current; /* current LLI being used */
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uint32_t cfg_lo;
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uint32_t cfg_hi;
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struct dw_dma_ptr_data ptr_data; /* pointer data */
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dma_callback_t dma_blkcallback;
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void *blkuser_data;
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dma_callback_t dma_tfrcallback;
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void *tfruser_data;
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};
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/* use array to get burst_elems for specific slot number setting.
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* the relation between msize and burst_elems should be
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* 2 ^ msize = burst_elems
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*/
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static const uint32_t burst_elems[] = {1, 2, 4, 8};
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/* Device run time data */
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struct dw_dma_dev_data {
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struct dma_context dma_ctx;
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struct dw_drv_plat_data *channel_data;
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struct dw_dma_chan_data chan[DW_CHAN_COUNT];
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struct dw_lli lli_pool[DW_CHAN_COUNT][CONFIG_DMA_DW_LLI_POOL_SIZE] __aligned(64);
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ATOMIC_DEFINE(channels_atomic, DW_CHAN_COUNT);
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};
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/* Device constant configuration parameters */
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struct dw_dma_dev_cfg {
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uintptr_t base;
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void (*irq_config)(void);
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};
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static ALWAYS_INLINE void dw_write(uintptr_t dma_base, uint32_t reg, uint32_t value)
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{
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*((volatile uint32_t *)(dma_base + reg)) = value;
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}
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static ALWAYS_INLINE uint32_t dw_read(uintptr_t dma_base, uint32_t reg)
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{
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return *((volatile uint32_t *)(dma_base + reg));
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}
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int dw_dma_setup(const struct device *dev);
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int dw_dma_config(const struct device *dev, uint32_t channel,
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struct dma_config *cfg);
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int dw_dma_reload(const struct device *dev, uint32_t channel,
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uint32_t src, uint32_t dst, size_t size);
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int dw_dma_start(const struct device *dev, uint32_t channel);
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int dw_dma_stop(const struct device *dev, uint32_t channel);
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int dw_dma_suspend(const struct device *dev, uint32_t channel);
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int dw_dma_resume(const struct device *dev, uint32_t channel);
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void dw_dma_isr(const struct device *dev);
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int dw_dma_get_status(const struct device *dev, uint32_t channel,
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struct dma_status *stat);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_DMA_DMA_DW_COMMON_H_ */
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