5ca33e20a8
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
92 lines
3 KiB
C
92 lines
3 KiB
C
/* ssd16xx_regs.h - Registers definition for SSD16XX compatible controller */
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/*
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* Copyright (c) 2018 PHYTEC Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SSD16XX_REGS_H__
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#define __SSD16XX_REGS_H__
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#define SSD16XX_CMD_GDO_CTRL 0x01
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#define SSD16XX_CMD_GDV_CTRL 0x03
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#define SSD16XX_CMD_SDV_CTRL 0x04
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#define SSD16XX_CMD_SOFTSTART 0x0c
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#define SSD16XX_CMD_GSCAN_START 0x0f
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#define SSD16XX_CMD_SLEEP_MODE 0x10
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#define SSD16XX_CMD_ENTRY_MODE 0x11
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#define SSD16XX_CMD_SW_RESET 0x12
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#define SSD16XX_CMD_TSENSOR_SELECTION 0x18
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#define SSD16XX_CMD_TSENS_CTRL 0x1a
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#define SSD16XX_CMD_READ_TSENS_CTRL 0x1b
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#define SSD16XX_CMD_MASTER_ACTIVATION 0x20
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#define SSD16XX_CMD_UPDATE_CTRL1 0x21
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#define SSD16XX_CMD_UPDATE_CTRL2 0x22
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#define SSD16XX_CMD_WRITE_RAM 0x24
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#define SSD16XX_CMD_WRITE_RED_RAM 0x26
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#define SSD16XX_CMD_READ_RAM 0x27
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#define SSD16XX_CMD_VCOM_SENSE 0x28
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#define SSD16XX_CMD_VCOM_SENSE_DURATON 0x29
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#define SSD16XX_CMD_PRGM_VCOM_OTP 0x2a
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#define SSD16XX_CMD_VCOM_VOLTAGE 0x2c
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#define SSD16XX_CMD_READ_OTP_REG 0x2d
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#define SSD16XX_CMD_READ_USER_ID 0x2e
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#define SSD16XX_CMD_READ_STATUS 0x2f
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#define SSD16XX_CMD_PRGM_WS_OTP 0x30
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#define SSD16XX_CMD_LOAD_WS_OTP 0x31
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#define SSD16XX_CMD_UPDATE_LUT 0x32
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#define SSD16XX_CMD_PRGM_OTP_SELECTION 0x36
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#define SSD16XX_CMD_OTP_SELECTION_CTRL 0x37
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#define SSD16XX_CMD_DUMMY_LINE 0x3a
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#define SSD16XX_CMD_GATE_LINE_WIDTH 0x3b
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#define SSD16XX_CMD_BWF_CTRL 0x3c
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#define SSD16XX_CMD_RAM_READ_CTRL 0x41
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#define SSD16XX_CMD_RAM_XPOS_CTRL 0x44
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#define SSD16XX_CMD_RAM_YPOS_CTRL 0x45
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#define SSD16XX_CMD_RAM_XPOS_CNTR 0x4e
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#define SSD16XX_CMD_RAM_YPOS_CNTR 0x4f
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/* Data entry sequence modes */
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#define SSD16XX_DATA_ENTRY_MASK 0x07
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#define SSD16XX_DATA_ENTRY_XDYDX 0x00
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#define SSD16XX_DATA_ENTRY_XIYDX 0x01
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#define SSD16XX_DATA_ENTRY_XDYIX 0x02
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#define SSD16XX_DATA_ENTRY_XIYIX 0x03
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#define SSD16XX_DATA_ENTRY_XDYDY 0x04
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#define SSD16XX_DATA_ENTRY_XIYDY 0x05
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#define SSD16XX_DATA_ENTRY_XDYIY 0x06
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#define SSD16XX_DATA_ENTRY_XIYIY 0x07
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/* Options for display update */
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#define SSD16XX_CTRL1_INITIAL_UPDATE_LL 0x00
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#define SSD16XX_CTRL1_INITIAL_UPDATE_LH 0x01
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#define SSD16XX_CTRL1_INITIAL_UPDATE_HL 0x02
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#define SSD16XX_CTRL1_INITIAL_UPDATE_HH 0x03
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/* Options for display update sequence */
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#define SSD16XX_CTRL2_ENABLE_CLK 0x80
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#define SSD16XX_CTRL2_ENABLE_ANALOG 0x40
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#define SSD16XX_CTRL2_LOAD_TEMPERATURE 0x20
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#define SSD16XX_CTRL2_LOAD_LUT 0x10
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#define SSD16XX_CTRL2_DISABLE_ANALOG 0x02
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#define SSD16XX_CTRL2_DISABLE_CLK 0x01
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#define SSD16XX_GEN1_CTRL2_TO_INITIAL 0x08
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#define SSD16XX_GEN1_CTRL2_TO_PATTERN 0x04
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#define SSD16XX_GEN2_CTRL2_MODE2 0x08
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#define SSD16XX_GEN2_CTRL2_DISPLAY 0x04
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#define SSD16XX_SLEEP_MODE_DSM 0x01
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#define SSD16XX_SLEEP_MODE_PON 0x00
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#define SSD16XX_RAM_READ_CTRL_BLACK 0
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#define SSD16XX_RAM_READ_CTRL_RED 1
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/* time constants in ms */
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#define SSD16XX_RESET_DELAY 1
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#define SSD16XX_BUSY_DELAY 1
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#endif /* __SSD16XX_REGS_H__ */
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