c64a74e711
Adapt all Espressif SoC and driver code to the updated hal_espressif module synced with IDF master branch. Main changes: - clock control: delegate peripheral clock gating to HAL layer using new clock/reset APIs - SPI/GDMA: adapt to restructured DMA HAL with new channel allocation and configuration interfaces - ethernet: add RMII clock configuration and PHY management - GPIO: simplify using direct HAL function calls - flash: adapt to updated SPI flash HAL interfaces - linker scripts: update IRAM/DRAM mappings for new HAL object files - DTS: fix ESP32-S2 PSRAM dcache1 address to match actual MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000 DPORT which lacks 8-bit access capability) - west.yml: update hal_espressif revision Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_dac
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#include <soc.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/dac.h>
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#include <zephyr/drivers/clock_control.h>
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#include <hal/dac_ll.h>
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#include <hal/dac_types.h>
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#include <hal/rtc_io_types.h>
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#include <hal/rtc_io_hal.h>
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#include <hal/rtc_io_ll.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(esp32_dac, CONFIG_DAC_LOG_LEVEL);
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struct dac_esp32_config {
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int irq_source;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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};
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static int dac_esp32_write_value(const struct device *dev,
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uint8_t channel, uint32_t value)
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{
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ARG_UNUSED(dev);
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dac_ll_update_output_value(channel, (uint8_t)value);
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return 0;
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}
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static int dac_esp32_channel_setup(const struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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ARG_UNUSED(dev);
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if (channel_cfg->channel_id >= SOC_DAC_CHAN_NUM) {
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LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
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return -EINVAL;
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}
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if (channel_cfg->internal) {
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LOG_ERR("Internal channels not supported");
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return -ENOTSUP;
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}
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dac_ll_power_on(channel_cfg->channel_id);
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return 0;
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}
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static int dac_esp32_init(const struct device *dev)
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{
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const struct dac_esp32_config *cfg = dev->config;
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if (!cfg->clock_dev) {
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LOG_ERR("Clock device missing");
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return -EINVAL;
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}
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if (!device_is_ready(cfg->clock_dev)) {
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LOG_ERR("Clock device not ready");
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return -ENODEV;
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}
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if (clock_control_on(cfg->clock_dev, (clock_control_subsys_t)cfg->clock_subsys) != 0) {
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LOG_ERR("DAC clock setup failed (%d)", -EIO);
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return -EIO;
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}
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return 0;
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}
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static DEVICE_API(dac, dac_esp32_driver_api) = {
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.channel_setup = dac_esp32_channel_setup,
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.write_value = dac_esp32_write_value
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};
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#define ESP32_DAC_INIT(id) \
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\
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static const struct dac_esp32_config dac_esp32_config_##id = { \
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.irq_source = DT_INST_IRQN(id), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
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.clock_subsys = (clock_control_subsys_t) DT_INST_CLOCKS_CELL(id, offset), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(id, \
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&dac_esp32_init, \
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NULL, \
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NULL, \
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&dac_esp32_config_##id, \
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POST_KERNEL, \
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CONFIG_DAC_INIT_PRIORITY, \
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&dac_esp32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(ESP32_DAC_INIT);
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