6b532ff43e
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t) Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
533 lines
16 KiB
C
533 lines
16 KiB
C
/*
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* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
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* Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_timer
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/gd32.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/atomic.h>
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#include <gd32_timer.h>
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LOG_MODULE_REGISTER(counter_gd32_timer);
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#define TIMER_INT_CH(ch) (TIMER_INT_CH0 << ch)
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#define TIMER_FLAG_CH(ch) (TIMER_FLAG_CH0 << ch)
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#define TIMER_INT_ALL (0xFFu)
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struct counter_gd32_ch_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_gd32_data {
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counter_top_callback_t top_cb;
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void *top_user_data;
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uint32_t guard_period;
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atomic_t cc_int_pending;
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uint32_t freq;
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struct counter_gd32_ch_data alarm[];
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};
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struct counter_gd32_config {
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struct counter_config_info counter_info;
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uint32_t reg;
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uint16_t clkid;
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struct reset_dt_spec reset;
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uint16_t prescaler;
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void (*irq_config)(const struct device *dev);
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void (*set_irq_pending)(void);
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uint32_t (*get_irq_pending)(void);
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};
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static uint32_t get_autoreload_value(const struct device *dev)
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{
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const struct counter_gd32_config *config = dev->config;
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return TIMER_CAR(config->reg);
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}
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static void set_autoreload_value(const struct device *dev, uint32_t value)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_CAR(config->reg) = value;
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}
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static uint32_t get_counter(const struct device *dev)
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{
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const struct counter_gd32_config *config = dev->config;
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return TIMER_CNT(config->reg);
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}
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static void set_counter(const struct device *dev, uint32_t value)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_CNT(config->reg) = value;
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}
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static void set_software_event_gen(const struct device *dev, uint8_t evt)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_SWEVG(config->reg) |= evt;
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}
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static void set_prescaler(const struct device *dev, uint16_t prescaler)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_PSC(config->reg) = prescaler;
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}
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static void set_compare_value(const struct device *dev, uint16_t chan,
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uint32_t compare_value)
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{
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const struct counter_gd32_config *config = dev->config;
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switch (chan) {
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case 0:
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TIMER_CH0CV(config->reg) = compare_value;
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break;
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case 1:
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TIMER_CH1CV(config->reg) = compare_value;
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break;
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case 2:
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TIMER_CH2CV(config->reg) = compare_value;
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break;
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case 3:
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TIMER_CH3CV(config->reg) = compare_value;
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break;
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}
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}
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static void interrupt_enable(const struct device *dev, uint32_t interrupt)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_DMAINTEN(config->reg) |= interrupt;
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}
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static void interrupt_disable(const struct device *dev, uint32_t interrupt)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_DMAINTEN(config->reg) &= ~interrupt;
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}
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static uint32_t interrupt_flag_get(const struct device *dev, uint32_t interrupt)
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{
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const struct counter_gd32_config *config = dev->config;
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return (TIMER_DMAINTEN(config->reg) & TIMER_INTF(config->reg) &
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interrupt);
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}
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static void interrupt_flag_clear(const struct device *dev, uint32_t interrupt)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_INTF(config->reg) &= ~interrupt;
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}
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static int counter_gd32_timer_start(const struct device *dev)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_CTL0(config->reg) |= (uint32_t)TIMER_CTL0_CEN;
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return 0;
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}
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static int counter_gd32_timer_stop(const struct device *dev)
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{
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const struct counter_gd32_config *config = dev->config;
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TIMER_CTL0(config->reg) &= ~(uint32_t)TIMER_CTL0_CEN;
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return 0;
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}
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static int counter_gd32_timer_get_value(const struct device *dev,
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uint32_t *ticks)
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{
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*ticks = get_counter(dev);
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return 0;
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}
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static uint32_t counter_gd32_timer_get_top_value(const struct device *dev)
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{
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return get_autoreload_value(dev);
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}
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static uint32_t ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
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{
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uint32_t to_top;
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if (likely(IS_BIT_MASK(top))) {
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return (val1 + val2) & top;
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}
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to_top = top - val1;
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return (val2 <= to_top) ? val1 + val2 : val2 - to_top;
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}
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static uint32_t ticks_sub(uint32_t val, uint32_t old, uint32_t top)
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{
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if (likely(IS_BIT_MASK(top))) {
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return (val - old) & top;
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}
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/* if top is not 2^n-1 */
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return (val >= old) ? (val - old) : val + top + 1 - old;
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}
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static void set_cc_int_pending(const struct device *dev, uint8_t chan)
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{
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const struct counter_gd32_config *config = dev->config;
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struct counter_gd32_data *data = dev->data;
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atomic_or(&data->cc_int_pending, TIMER_INT_CH(chan));
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config->set_irq_pending();
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}
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static int set_cc(const struct device *dev, uint8_t chan, uint32_t val,
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uint32_t flags)
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{
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const struct counter_gd32_config *config = dev->config;
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struct counter_gd32_data *data = dev->data;
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__ASSERT_NO_MSG(data->guard_period <
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counter_gd32_timer_get_top_value(dev));
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bool absolute = flags & COUNTER_ALARM_CFG_ABSOLUTE;
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uint32_t top = counter_gd32_timer_get_top_value(dev);
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uint32_t now, diff, max_rel_val;
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bool irq_on_late;
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int err = 0;
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ARG_UNUSED(config);
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__ASSERT(!(TIMER_DMAINTEN(config->reg) & TIMER_INT_CH(chan)),
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"Expected that CC interrupt is disabled.");
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/* First take care of a risk of an event coming from CC being set to
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* next tick. Reconfigure CC to future (now tick is the furthest
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* future).
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*/
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now = get_counter(dev);
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set_compare_value(dev, chan, now);
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interrupt_flag_clear(dev, TIMER_FLAG_CH(chan));
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if (absolute) {
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max_rel_val = top - data->guard_period;
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irq_on_late = flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
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} else {
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/* If relative value is smaller than half of the counter range
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* it is assumed that there is a risk of setting value too late
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* and late detection algorithm must be applied. When late
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* setting is detected, interrupt shall be triggered for
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* immediate expiration of the timer. Detection is performed
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* by limiting relative distance between CC and counter.
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*
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* Note that half of counter range is an arbitrary value.
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*/
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irq_on_late = val < (top / 2);
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/* limit max to detect short relative being set too late. */
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max_rel_val = irq_on_late ? top / 2 : top;
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val = ticks_add(now, val, top);
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}
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set_compare_value(dev, chan, val);
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/* decrement value to detect also case when val == get_counter(dev).
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* Otherwise, condition would need to include comparing diff against 0.
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*/
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diff = ticks_sub(val - 1, get_counter(dev), top);
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if (diff > max_rel_val) {
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if (absolute) {
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err = -ETIME;
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}
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag.
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*/
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if (irq_on_late) {
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set_cc_int_pending(dev, chan);
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} else {
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data->alarm[chan].callback = NULL;
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}
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} else {
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interrupt_enable(dev, TIMER_INT_CH(chan));
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}
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return err;
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}
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static int
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counter_gd32_timer_set_alarm(const struct device *dev, uint8_t chan,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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struct counter_gd32_data *data = dev->data;
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struct counter_gd32_ch_data *chdata = &data->alarm[chan];
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if (alarm_cfg->ticks > counter_gd32_timer_get_top_value(dev)) {
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return -EINVAL;
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}
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if (chdata->callback) {
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return -EBUSY;
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}
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chdata->callback = alarm_cfg->callback;
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chdata->user_data = alarm_cfg->user_data;
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return set_cc(dev, chan, alarm_cfg->ticks, alarm_cfg->flags);
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}
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static int counter_gd32_timer_cancel_alarm(const struct device *dev,
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uint8_t chan)
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{
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struct counter_gd32_data *data = dev->data;
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interrupt_disable(dev, TIMER_INT_CH(chan));
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data->alarm[chan].callback = NULL;
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return 0;
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}
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static int counter_gd32_timer_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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const struct counter_gd32_config *config = dev->config;
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struct counter_gd32_data *data = dev->data;
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int err = 0;
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for (uint32_t i = 0; i < config->counter_info.channels; i++) {
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/* Overflow can be changed only when all alarms are
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* disables.
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*/
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if (data->alarm[i].callback) {
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return -EBUSY;
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}
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}
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interrupt_disable(dev, TIMER_INT_UP);
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set_autoreload_value(dev, cfg->ticks);
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interrupt_flag_clear(dev, TIMER_INT_FLAG_UP);
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data->top_cb = cfg->callback;
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data->top_user_data = cfg->user_data;
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if (!(cfg->flags & COUNTER_TOP_CFG_DONT_RESET)) {
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set_counter(dev, 0);
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} else if (get_counter(dev) >= cfg->ticks) {
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err = -ETIME;
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if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
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set_counter(dev, 0);
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}
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}
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if (cfg->callback) {
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interrupt_enable(dev, TIMER_INT_UP);
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}
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return err;
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}
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static uint32_t counter_gd32_timer_get_pending_int(const struct device *dev)
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{
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const struct counter_gd32_config *cfg = dev->config;
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return cfg->get_irq_pending();
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}
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static uint32_t counter_gd32_timer_get_freq(const struct device *dev)
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{
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struct counter_gd32_data *data = dev->data;
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return data->freq;
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}
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static uint32_t counter_gd32_timer_get_guard_period(const struct device *dev,
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uint32_t flags)
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{
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struct counter_gd32_data *data = dev->data;
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return data->guard_period;
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}
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static int counter_gd32_timer_set_guard_period(const struct device *dev,
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uint32_t guard, uint32_t flags)
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{
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struct counter_gd32_data *data = dev->data;
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__ASSERT_NO_MSG(guard < counter_gd32_timer_get_top_value(dev));
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data->guard_period = guard;
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return 0;
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}
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static void top_irq_handle(const struct device *dev)
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{
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struct counter_gd32_data *data = dev->data;
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counter_top_callback_t cb = data->top_cb;
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if (interrupt_flag_get(dev, TIMER_INT_FLAG_UP) != 0) {
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interrupt_flag_clear(dev, TIMER_INT_FLAG_UP);
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__ASSERT(cb != NULL, "top event enabled - expecting callback");
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cb(dev, data->top_user_data);
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}
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}
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static void alarm_irq_handle(const struct device *dev, uint32_t chan)
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{
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struct counter_gd32_data *data = dev->data;
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struct counter_gd32_ch_data *alarm = &data->alarm[chan];
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counter_alarm_callback_t cb;
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bool hw_irq_pending = !!(interrupt_flag_get(dev, TIMER_FLAG_CH(chan)));
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bool sw_irq_pending = data->cc_int_pending & TIMER_INT_CH(chan);
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if (hw_irq_pending || sw_irq_pending) {
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atomic_and(&data->cc_int_pending, ~TIMER_INT_CH(chan));
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interrupt_disable(dev, TIMER_INT_CH(chan));
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interrupt_flag_clear(dev, TIMER_FLAG_CH(chan));
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cb = alarm->callback;
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alarm->callback = NULL;
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if (cb) {
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cb(dev, chan, get_counter(dev), alarm->user_data);
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}
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}
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}
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static void irq_handler(const struct device *dev)
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{
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const struct counter_gd32_config *cfg = dev->config;
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top_irq_handle(dev);
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for (uint32_t i = 0; i < cfg->counter_info.channels; i++) {
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alarm_irq_handle(dev, i);
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}
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}
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static int counter_gd32_timer_init(const struct device *dev)
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{
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const struct counter_gd32_config *cfg = dev->config;
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struct counter_gd32_data *data = dev->data;
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uint32_t pclk;
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clock_control_on(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t)&cfg->clkid);
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clock_control_get_rate(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t)&cfg->clkid, &pclk);
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data->freq = pclk / (cfg->prescaler + 1);
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interrupt_disable(dev, TIMER_INT_ALL);
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reset_line_toggle_dt(&cfg->reset);
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cfg->irq_config(dev);
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set_prescaler(dev, cfg->prescaler);
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set_autoreload_value(dev, cfg->counter_info.max_top_value);
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set_software_event_gen(dev, TIMER_SWEVG_UPG);
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return 0;
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}
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static const struct counter_driver_api counter_api = {
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.start = counter_gd32_timer_start,
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.stop = counter_gd32_timer_stop,
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.get_value = counter_gd32_timer_get_value,
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.set_alarm = counter_gd32_timer_set_alarm,
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.cancel_alarm = counter_gd32_timer_cancel_alarm,
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.set_top_value = counter_gd32_timer_set_top_value,
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.get_pending_int = counter_gd32_timer_get_pending_int,
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.get_top_value = counter_gd32_timer_get_top_value,
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.get_guard_period = counter_gd32_timer_get_guard_period,
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.set_guard_period = counter_gd32_timer_set_guard_period,
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.get_freq = counter_gd32_timer_get_freq,
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};
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#define TIMER_IRQ_CONFIG(n) \
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static void irq_config_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, global, irq), \
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DT_INST_IRQ_BY_NAME(n, global, priority), \
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irq_handler, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, global, irq)); \
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} \
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static void set_irq_pending_##n(void) \
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{ \
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(NVIC_SetPendingIRQ(DT_INST_IRQ_BY_NAME(n, global, irq))); \
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} \
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static uint32_t get_irq_pending_##n(void) \
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{ \
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return NVIC_GetPendingIRQ( \
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DT_INST_IRQ_BY_NAME(n, global, irq)); \
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}
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#define TIMER_IRQ_CONFIG_ADVANCED(n) \
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static void irq_config_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT((DT_INST_IRQ_BY_NAME(n, up, irq)), \
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(DT_INST_IRQ_BY_NAME(n, up, priority)), \
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irq_handler, (DEVICE_DT_INST_GET(n)), 0); \
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irq_enable((DT_INST_IRQ_BY_NAME(n, up, irq))); \
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IRQ_CONNECT((DT_INST_IRQ_BY_NAME(n, cc, irq)), \
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(DT_INST_IRQ_BY_NAME(n, cc, priority)), \
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irq_handler, (DEVICE_DT_INST_GET(n)), 0); \
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irq_enable((DT_INST_IRQ_BY_NAME(n, cc, irq))); \
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} \
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static void set_irq_pending_##n(void) \
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{ \
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(NVIC_SetPendingIRQ(DT_INST_IRQ_BY_NAME(n, cc, irq))); \
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} \
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static uint32_t get_irq_pending_##n(void) \
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{ \
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return NVIC_GetPendingIRQ(DT_INST_IRQ_BY_NAME(n, cc, irq)); \
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}
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#define GD32_TIMER_INIT(n) \
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COND_CODE_1(DT_INST_PROP(n, is_advanced), \
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(TIMER_IRQ_CONFIG_ADVANCED(n)), (TIMER_IRQ_CONFIG(n))); \
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static struct counter_gd32_data_##n { \
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struct counter_gd32_data data; \
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struct counter_gd32_ch_data alarm[DT_INST_PROP(n, channels)]; \
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} timer_data_##n = {0}; \
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static const struct counter_gd32_config timer_config_##n = { \
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.counter_info = {.max_top_value = COND_CODE_1( \
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DT_INST_PROP(n, is_32bit), \
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(UINT32_MAX), (UINT16_MAX)), \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.freq = 0, \
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.channels = DT_INST_PROP(n, channels)}, \
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.reg = DT_INST_REG_ADDR(n), \
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.clkid = DT_INST_CLOCKS_CELL(n, id), \
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.reset = RESET_DT_SPEC_INST_GET(n), \
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.prescaler = DT_INST_PROP(n, prescaler), \
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.irq_config = irq_config_##n, \
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.set_irq_pending = set_irq_pending_##n, \
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.get_irq_pending = get_irq_pending_##n, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, counter_gd32_timer_init, NULL, \
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&timer_data_##n, &timer_config_##n, \
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PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY, \
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&counter_api);
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DT_INST_FOREACH_STATUS_OKAY(GD32_TIMER_INIT);
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