4a0032ddc1
In order to configure domain clock, clock_control_configure should be used instead of clock_control_on which is only useful for bus clock gating. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2022, Linaro Ltd
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*
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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#define DT_DRV_COMPAT st_stm32_clock_mux
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LOG_MODULE_REGISTER(clock_mux, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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struct stm32_clk_mux_config {
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const struct stm32_pclken pclken;
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};
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static int stm32_clk_mux_init(const struct device *dev)
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{
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const struct stm32_clk_mux_config *cfg = dev->config;
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if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &cfg->pclken, NULL) != 0) {
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LOG_ERR("Could not enable clock mux");
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return -EIO;
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}
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return 0;
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}
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#define STM32_MUX_CLK_INIT(id) \
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\
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static const struct stm32_clk_mux_config stm32_clk_mux_cfg_##id = { \
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.pclken = STM32_CLOCK_INFO(0, DT_DRV_INST(id)) \
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}; \
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\
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DEVICE_DT_INST_DEFINE(id, &stm32_clk_mux_init, NULL, \
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NULL, &stm32_clk_mux_cfg_##id, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,\
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(STM32_MUX_CLK_INIT)
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