5960c2d5a1
This commit updates the STM32Fx clock driver to add complete support for all PLLs for all SoCs. Supports all outputs and additional divisors: - PLL-DIV-R - PLLI2S-P - PLLI2S-DIV-Q - PLLI2S-DIV-R Adds global checks to make sure that all: - All PLLs share the same source clocks - All PLLs share the same M-Divisor (on applicable SoCs) - Both div-X and div-divX are defined (on applicable SoCs) Functions get_plli2s_source and get_plli2ssrc_frequency are added to make sure that PLLI2S can be used even if PLL is not defined. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
103 lines
3.1 KiB
C
103 lines
3.1 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
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#define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/util.h>
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#include <stm32_ll_utils.h>
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/* Macros to fill up multiplication and division factors values */
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#define pllm(v) CONCAT(LL_RCC_PLLM_DIV_, v)
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#define pllp(v) CONCAT(LL_RCC_PLLP_DIV_, v)
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#define pllq(v) CONCAT(LL_RCC_PLLQ_DIV_, v)
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#define pllr(v) CONCAT(LL_RCC_PLLR_DIV_, v)
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#define plldivr(v) CONCAT(LL_RCC_PLLDIVR_DIV_, v)
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#if defined(RCC_PLLI2SCFGR_PLLI2SM)
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/* Some stm32F4 devices have a dedicated PLL I2S with M divider */
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#define plli2sm(v) CONCAT(LL_RCC_PLLI2SM_DIV_, v)
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#else
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/* Some stm32F4 devices (typ. stm32F401) have a dedicated PLL I2S with PLL M divider */
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#define plli2sm(v) CONCAT(LL_RCC_PLLM_DIV_, v)
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#endif /* RCC_PLLI2SCFGR_PLLI2SM */
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#define plli2sp(v) CONCAT(LL_RCC_PLLI2SP_DIV_, v)
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#define plli2sq(v) CONCAT(LL_RCC_PLLI2SQ_DIV_, v)
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#define plli2sdivq(v) CONCAT(LL_RCC_PLLI2SDIVQ_DIV_, v)
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#define plli2sr(v) CONCAT(LL_RCC_PLLI2SR_DIV_, v)
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#define plli2sdivr(v) CONCAT(LL_RCC_PLLI2SDIVR_DIV_, v)
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#define pllsaim(v) CONCAT(LL_RCC_PLLM_DIV_, v)
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#define pllsaip(v) CONCAT(LL_RCC_PLLSAIP_DIV_, v)
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#define pllsaiq(v) CONCAT(LL_RCC_PLLSAIQ_DIV_, v)
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#define pllsaidivq(v) CONCAT(LL_RCC_PLLSAIDIVQ_DIV_, v)
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#define pllsair(v) CONCAT(LL_RCC_PLLSAIR_DIV_, v)
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#define pllsaidivr(v) CONCAT(LL_RCC_PLLSAIDIVR_DIV_, v)
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#define pllsai1p(v) CONCAT(LL_RCC_PLLSAI1P_DIV_, v)
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#define pllsai1q(v) CONCAT(LL_RCC_PLLSAI1Q_DIV_, v)
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#define pllsai1r(v) CONCAT(LL_RCC_PLLSAI1R_DIV_, v)
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#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
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#define pllsai2m(v) CONCAT(LL_RCC_PLLSAI2M_DIV_, v)
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#else
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#define pllsai2m(v) CONCAT(LL_RCC_PLLM_DIV_, v)
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#endif
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#define pllsai2p(v) CONCAT(LL_RCC_PLLSAI2P_DIV_, v)
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#define pllsai2q(v) CONCAT(LL_RCC_PLLSAI2Q_DIV_, v)
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#define pllsai2r(v) CONCAT(LL_RCC_PLLSAI2R_DIV_, v)
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#define pllsai2divr(v) CONCAT(LL_RCC_PLLSAI2DIVR_DIV_, v)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32_PLL_ENABLED)
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void config_pll_sysclock(void);
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uint32_t get_pllout_frequency(void);
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uint32_t get_pllsrc_frequency(void);
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#endif
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#if defined(STM32_PLL2_ENABLED)
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void config_pll2(void);
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#endif
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#if defined(STM32_PLLI2S_ENABLED)
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uint32_t get_plli2ssrc_frequency(void);
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void config_plli2s(void);
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#endif
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#if defined(STM32_PLLSAI_ENABLED)
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uint32_t get_pllsaisrc_frequency(void);
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void config_pllsai(void);
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#endif
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#if defined(STM32_PLLSAI1_ENABLED)
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uint32_t get_pllsai1src_frequency(void);
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void config_pllsai1(void);
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#endif
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#if defined(STM32_PLLSAI2_ENABLED)
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uint32_t get_pllsai2src_frequency(void);
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void config_pllsai2(void);
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#endif
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void config_enable_default_clocks(void);
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void config_regulator_voltage(uint32_t hclk_freq);
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int enabled_clock(uint32_t src_clk);
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#if defined(STM32_CK48_ENABLED)
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uint32_t get_ck48_frequency(void);
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#endif
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/* functions exported to the soc power.c */
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int stm32_clock_control_init(const struct device *dev);
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void stm32_clock_control_standby_exit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */
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