d2e79866ad
Remove old unused defines from header Use clang-format to apply coding guideline to r8a7795 driver Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
/*
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* Copyright (c) 2022-2023 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
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#define ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/device_mmio.h>
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#define CPG_NUM_DOMAINS 2
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struct cpg_clk_info_table {
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uint32_t domain;
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uint32_t module;
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mem_addr_t offset;
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uint32_t parent_id;
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int64_t in_freq;
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int64_t out_freq;
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/* TODO: add setting of this field and add function for getting status */
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enum clock_control_status status;
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struct cpg_clk_info_table *parent;
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struct cpg_clk_info_table *children_list;
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struct cpg_clk_info_table *next_sibling;
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};
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struct rcar_cpg_mssr_data {
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DEVICE_MMIO_RAM; /* Must be first */
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struct cpg_clk_info_table *clk_info_table[CPG_NUM_DOMAINS];
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const uint32_t clk_info_table_size[CPG_NUM_DOMAINS];
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struct k_spinlock lock;
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uint32_t (*get_div_helper)(uint32_t reg, uint32_t module);
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int (*set_rate_helper)(uint32_t module, uint32_t *div, uint32_t *div_mask);
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};
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#define RCAR_CPG_NONE -1
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#define RCAR_CPG_KHZ(khz) ((khz) * 1000U)
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#define RCAR_CPG_MHZ(mhz) (RCAR_CPG_KHZ(mhz) * 1000U)
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#define RCAR_CORE_CLK_INFO_ITEM(id, off, par_id, in_frq) \
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{ \
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.domain = CPG_CORE, \
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.module = id, \
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.offset = off, \
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.parent_id = par_id, \
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.in_freq = in_frq, \
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.out_freq = RCAR_CPG_NONE, \
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.status = CLOCK_CONTROL_STATUS_UNKNOWN, \
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.parent = NULL, \
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.children_list = NULL, \
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.next_sibling = NULL, \
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}
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#define RCAR_MOD_CLK_INFO_ITEM(id, par_id) \
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{ \
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.domain = CPG_MOD, \
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.module = id, \
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.offset = RCAR_CPG_NONE, \
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.parent_id = par_id, \
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.in_freq = RCAR_CPG_NONE, \
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.out_freq = RCAR_CPG_NONE, \
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.status = CLOCK_CONTROL_STATUS_UNKNOWN, \
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.parent = NULL, \
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.children_list = NULL, \
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.next_sibling = NULL, \
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}
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#ifdef CONFIG_SOC_SERIES_RCAR_GEN3
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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/* CPG write protect offset */
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#define CPGWPR 0x900
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/* Realtime Module Stop Control Register offsets */
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static const uint16_t mstpcr[] = {
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0x110, 0x114, 0x118, 0x11c,
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0x120, 0x124, 0x128, 0x12c,
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0x980, 0x984, 0x988, 0x98c,
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};
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/* Software Reset Register offsets */
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static const uint16_t srcr[] = {
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0x0A0, 0x0A8, 0x0B0, 0x0B8,
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0x0BC, 0x0C4, 0x1C8, 0x1CC,
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0x920, 0x924, 0x928, 0x92C,
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};
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#elif defined(CONFIG_SOC_SERIES_RCAR_GEN4)
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x2C80 + (i) * 4)
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/* CPG write protect offset */
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#define CPGWPR 0x0
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/* Realtime Module Stop Control Register offsets */
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static const uint16_t mstpcr[] = {
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0x2D00, 0x2D04, 0x2D08, 0x2D0C,
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0x2D10, 0x2D14, 0x2D18, 0x2D1C,
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0x2D20, 0x2D24, 0x2D28, 0x2D2C,
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0x2D30, 0x2D34, 0x2D38, 0x2D3C,
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0x2D40, 0x2D44, 0x2D48, 0x2D4C,
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0x2D50, 0x2D54, 0x2D58, 0x2D5C,
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0x2D60, 0x2D64, 0x2D68, 0x2D6C,
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};
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/* Software Reset Register offsets */
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static const uint16_t srcr[] = {
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0x2C00, 0x2C04, 0x2C08, 0x2C0C,
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0x2C10, 0x2C14, 0x2C18, 0x2C1C,
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0x2C20, 0x2C24, 0x2C28, 0x2C2C,
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0x2C30, 0x2C34, 0x2C38, 0x2C3C,
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0x2C40, 0x2C44, 0x2C48, 0x2C4C,
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0x2C50, 0x2C54, 0x2C58, 0x2C5C,
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0x2C60, 0x2C64, 0x2C68, 0x2C6C,
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};
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#endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */
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void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);
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int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable);
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struct cpg_clk_info_table *rcar_cpg_find_clk_info_by_module_id(const struct device *dev,
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uint32_t domain,
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uint32_t id);
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void rcar_cpg_build_clock_relationship(const struct device *dev);
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void rcar_cpg_update_all_in_out_freq(const struct device *dev);
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int rcar_cpg_get_rate(const struct device *dev, clock_control_subsys_t sys, uint32_t *rate);
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int rcar_cpg_set_rate(const struct device *dev, clock_control_subsys_t sys,
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clock_control_subsys_rate_t rate);
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#endif /* ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_ */
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