139fcfa5f7
This patch add supports for performing clock-related operations on i.MX8ULP. This consists of: 1) Adding a LUT. 2) Adding an initialization function meant to tell the HAL which rate the XTALs on the boards (EVK and EVK9) run at. This is used by the functions that compute the rate of an IP clock. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
154 lines
3.4 KiB
C
154 lines
3.4 KiB
C
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* Based on clock_control_rv32m1_pcc.c, which is:
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* Copyright (c) 2018 Foundries.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_kinetis_pcc
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#include <errno.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <fsl_clock.h>
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control_mcux_pcc);
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struct mcux_pcc_config {
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uint32_t base_address;
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uint32_t *clocks;
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uint32_t clock_num;
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};
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#define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address)
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#ifndef MAKE_PCC_REGADDR
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#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
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#endif
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static inline int get_clock_encoding(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *clock_encoding)
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{
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const struct mcux_pcc_config *cfg;
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uint32_t clock_name;
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cfg = dev->config;
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clock_name = POINTER_TO_UINT(sub_system);
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if (!cfg->clock_num) {
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*clock_encoding = MAKE_PCC_REGADDR(DEV_BASE(dev), clock_name);
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return 0;
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}
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/* sanity check */
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if (clock_name >= cfg->clock_num) {
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return -EINVAL;
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}
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*clock_encoding = cfg->clocks[clock_name];
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return 0;
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}
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static int mcux_pcc_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t clock_encoding;
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int ret;
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ret = get_clock_encoding(dev, sub_system, &clock_encoding);
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if (ret < 0) {
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return ret;
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}
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CLOCK_EnableClock(clock_encoding);
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return 0;
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}
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static int mcux_pcc_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t clock_encoding;
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int ret;
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ret = get_clock_encoding(dev, sub_system, &clock_encoding);
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if (ret < 0) {
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return ret;
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}
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CLOCK_DisableClock(clock_encoding);
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return 0;
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}
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static int mcux_pcc_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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uint32_t clock_encoding;
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int ret;
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ret = get_clock_encoding(dev, sub_system, &clock_encoding);
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if (ret < 0) {
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return ret;
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}
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*rate = CLOCK_GetIpFreq(clock_encoding);
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return 0;
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}
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static const struct clock_control_driver_api mcux_pcc_api = {
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.on = mcux_pcc_on,
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.off = mcux_pcc_off,
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.get_rate = mcux_pcc_get_rate,
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};
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static int mcux_pcc_init(const struct device *dev)
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{
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#ifdef CONFIG_SOC_MIMX8UD7
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/* 8ULP's XTAL is set to 24MHz on EVK9. We keep
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* this as SOC level because this should also be
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* the case for the EVK board.
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*/
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CLOCK_SetXtal0Freq(24000000);
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#endif /* CONFIG_SOC_MIMX8UD7 */
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return 0;
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}
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#ifdef CONFIG_SOC_MIMX8UD7
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static uint32_t clocks[] = {
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/* clocks managed through PCC4 */
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kCLOCK_Lpuart7,
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};
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#else
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/* this is empty for SOCs which don't need a translation from
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* the clock ID passed through the DTS and the clock ID encoding
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* from the HAL. For these SOCs, the clock ID will be built based
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* on the value passed from the DTS and the PCC base.
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*/
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static uint32_t clocks[] = {};
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#endif /* CONFIG_SOC_MIMX8UD7 */
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#define MCUX_PCC_INIT(inst) \
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static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
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.base_address = DT_INST_REG_ADDR(inst), \
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.clocks = clocks, \
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.clock_num = ARRAY_SIZE(clocks), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&mcux_pcc_init, \
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NULL, \
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NULL, &mcux_pcc##inst##_config, \
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PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
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&mcux_pcc_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_PCC_INIT)
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