193ad777f4
Several STM32 variants include both shared IRQs for some ADCs and separate IRQs for others (for example, STM32G473 has 5 ADCs, ADC1 and ADC2 share one IRQ while ADC3, ADC4 and ADC5 each have unique IRQs). The STM32 ADC driver however previously only supported either separate IRQ lines for each operational ADC in the devicetree or a single shared IRQ for all operational ADCs in the devicetree which prevented all ADCs from being usable at the same time when the variant contained a mix of both shared and separate ADC IRQ lines (only either all the shared or all the separate and one of the shared might be used at most for one application). To allow for all ADCs in an STM32 variant to be usable in a single application, generate an ISR and initialization function for each unique IRQn as defined in the devicetree and give the task of initialization to the first ADC which connects to that particular IRQ. Each ISR function will generate code to call the ISR for each ADC associated with that IRQn as was previously done for CONFIG_ADC_STM32_SHARED_IRQS, allowing an ISR to be shared for the ADCs sharing an IRQ while simultaneously providing separate ISRs for each IRQ. Thus, the only information required to have ADCs either share an ISR or not is provided by the devicetree. Signed-off-by: Michael R Rosen <mrrosen@alumni.cmu.edu>
27 lines
659 B
Plaintext
27 lines
659 B
Plaintext
# ADC configuration options
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# Copyright (c) 2019 Intel Corporation
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# Copyright (c) 2019 Endre Karlson
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# Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
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# Copyright (c) 2021 Marius Scholtz, RIC Electronics
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# Copyright (c) 2022 Hein Wessels, Nobleo Technology
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# SPDX-License-Identifier: Apache-2.0
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config ADC_STM32
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bool "STM32 ADC driver"
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default y
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depends on DT_HAS_ST_STM32_ADC_ENABLED
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help
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Enable the driver implementation for the stm32xx ADC
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if ADC_STM32
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config ADC_STM32_DMA
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bool "STM32 MCU ADC DMA Support"
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select DMA
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help
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Enable the ADC DMA mode for ADC instances
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that enable dma channels in their device tree node.
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endif
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