681a42fc5a
The interrupts generated by the generic timer behave in a level-sensitive manner. Change the DT to reflect the same. Fixes: #25585 Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
85 lines
1.8 KiB
Plaintext
85 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Derived from DTS extracted with:
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*
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* qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
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* -machine dumpdtb=virt.dtb
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*
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* dtc -I dtb -O dts virt.dtb
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*/
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#include <mem.h>
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#include <arm/armv8-a.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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};
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@8000000 {
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compatible = "arm,gic";
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reg = <0x8000000 0x10000>,
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<0x8010000 0x10000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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uart0: uart@9000000 {
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compatible = "arm,pl011";
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reg = <0x9000000 0x1000>;
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status = "disabled";
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL 0>;
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interrupt-names = "irq_0";
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clocks = <&uartclk>;
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label = "UART_0";
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};
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flash0: flash@0 {
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compatible = "cfi-flash";
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bank-width = <4>;
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/* As this is pointed to by zephyr,flash we can only handle
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* one value in the reg property, so we comment out the
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* second flash bank for now
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*/
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reg = <0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>;
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};
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arch_timer: timer {
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compatible = "arm,arm-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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label = "arch_timer";
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};
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};
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};
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