ab2d73379a
Conditionalizes serial pinmuxes on CONFIG_SERIAL for all nxp boards (kinetis, lpc, and imx families) to avoid possible conflicts between peripherals. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include "device_imx.h"
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static int udoo_neo_full_m4_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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/* GPIO4_IO06 pin mux configuration (red LED) */
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 =
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(5);
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 =
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(6);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart5), okay) && CONFIG_SERIAL
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/* UART5 pin mux configuration */
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 =
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(2);
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 =
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IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(2);
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 =
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(6) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_MASK;
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 =
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(6) |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_MASK;
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IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT =
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IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(0);
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#endif
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return 0;
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}
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SYS_INIT(udoo_neo_full_m4_init, PRE_KERNEL_1, 0);
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