As a slow FPGA platform with max. freq < 25 Mhz, the default CON_SYS_CLOCK_TICKS_PER_SEC=10000 is not suitable. CON_SYS_CLOCK_TICKS_PER_SEC=100 is a better value. Signed-off-by: Wayne Ren <wei.ren@synopsys.com> |
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em_starterkit | ||
emsdp | ||
hsdk | ||
iotdk | ||
nsim | ||
index.rst |