bbe5e1e6eb
Namespaced the generated headers with `zephyr` to prevent potential conflict with other headers. Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH` that is enabled by default. This allows the developers to continue the use of the old include paths for the time being until it is deprecated and eventually removed. The Kconfig will generate a build-time warning message, similar to the `CONFIG_TIMER_RANDOM_GENERATOR`. Updated the includes path of in-tree sources accordingly. Most of the changes here are scripted, check the PR for more info. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
794 lines
22 KiB
C
794 lines
22 KiB
C
/**
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* @file
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*
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* @brief Public APIs for the DMA drivers.
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*/
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_H_
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#define ZEPHYR_INCLUDE_DRIVERS_DMA_H_
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief DMA Interface
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* @defgroup dma_interface DMA Interface
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* @since 1.5
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* @version 1.0.0
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* @ingroup io_interfaces
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* @{
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*/
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/**
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* @brief DMA channel direction
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*/
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enum dma_channel_direction {
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/** Memory to memory */
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MEMORY_TO_MEMORY = 0x0,
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/** Memory to peripheral */
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MEMORY_TO_PERIPHERAL,
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/** Peripheral to memory */
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PERIPHERAL_TO_MEMORY,
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/** Peripheral to peripheral */
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PERIPHERAL_TO_PERIPHERAL,
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/** Host to memory */
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HOST_TO_MEMORY,
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/** Memory to host */
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MEMORY_TO_HOST,
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/**
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* Number of all common channel directions.
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*/
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DMA_CHANNEL_DIRECTION_COMMON_COUNT,
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/**
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* This and higher values are dma controller or soc specific.
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* Refer to the specified dma driver header file.
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*/
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DMA_CHANNEL_DIRECTION_PRIV_START = DMA_CHANNEL_DIRECTION_COMMON_COUNT,
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/**
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* Maximum allowed value (3 bit field!)
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*/
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DMA_CHANNEL_DIRECTION_MAX = 0x7
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};
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/**
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* @brief DMA address adjustment
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*
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* Valid values for @a source_addr_adj and @a dest_addr_adj
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*/
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enum dma_addr_adj {
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/** Increment the address */
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DMA_ADDR_ADJ_INCREMENT,
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/** Decrement the address */
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DMA_ADDR_ADJ_DECREMENT,
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/** No change the address */
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DMA_ADDR_ADJ_NO_CHANGE,
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};
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/**
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* @brief DMA channel attributes
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*/
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enum dma_channel_filter {
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DMA_CHANNEL_NORMAL, /* normal DMA channel */
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DMA_CHANNEL_PERIODIC, /* can be triggered by periodic sources */
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};
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/**
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* @brief DMA attributes
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*/
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enum dma_attribute_type {
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DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT,
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DMA_ATTR_BUFFER_SIZE_ALIGNMENT,
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DMA_ATTR_COPY_ALIGNMENT,
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DMA_ATTR_MAX_BLOCK_COUNT,
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};
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/**
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* @struct dma_block_config
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* @brief DMA block configuration structure.
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*
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* Aside from source address, destination address, and block size many of these options are hardware
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* and driver dependent.
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*/
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struct dma_block_config {
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#ifdef CONFIG_DMA_64BIT
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/** block starting address at source */
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uint64_t source_address;
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/** block starting address at destination */
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uint64_t dest_address;
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#else
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/** block starting address at source */
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uint32_t source_address;
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/** block starting address at destination */
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uint32_t dest_address;
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#endif
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/** Address adjustment at gather boundary */
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uint32_t source_gather_interval;
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/** Address adjustment at scatter boundary */
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uint32_t dest_scatter_interval;
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/** Continuous transfer count between scatter boundaries */
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uint16_t dest_scatter_count;
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/** Continuous transfer count between gather boundaries */
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uint16_t source_gather_count;
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/** Number of bytes to be transferred for this block */
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uint32_t block_size;
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/** Pointer to next block in a transfer list */
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struct dma_block_config *next_block;
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/** Enable source gathering when set to 1 */
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uint16_t source_gather_en : 1;
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/** Enable destination scattering when set to 1 */
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uint16_t dest_scatter_en : 1;
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/**
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* Source address adjustment option
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*
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* - 0b00 increment
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* - 0b01 decrement
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* - 0b10 no change
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*/
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uint16_t source_addr_adj : 2;
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/**
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* Destination address adjustment
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*
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* - 0b00 increment
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* - 0b01 decrement
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* - 0b10 no change
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*/
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uint16_t dest_addr_adj : 2;
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/** Reload source address at the end of block transfer */
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uint16_t source_reload_en : 1;
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/** Reload destination address at the end of block transfer */
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uint16_t dest_reload_en : 1;
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/** FIFO fill before starting transfer, HW specific meaning */
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uint16_t fifo_mode_control : 4;
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/**
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* Transfer flow control mode
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*
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* - 0b0 source request service upon data availability
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* - 0b1 source request postponed until destination request happens
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*/
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uint16_t flow_control_mode : 1;
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uint16_t _reserved : 3;
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};
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/** The DMA callback event has occurred at the completion of a transfer list */
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#define DMA_STATUS_COMPLETE 0
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/** The DMA callback has occurred at the completion of a single transfer block in a transfer list */
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#define DMA_STATUS_BLOCK 1
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/**
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* @typedef dma_callback_t
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* @brief Callback function for DMA transfer completion
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*
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* If enabled, callback function will be invoked at transfer or block completion,
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* or when an error happens.
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* In circular mode, @p status indicates that the DMA device has reached either
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* the end of the buffer (DMA_STATUS_COMPLETE) or a water mark (DMA_STATUS_BLOCK).
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*
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* @param dev Pointer to the DMA device calling the callback.
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* @param user_data A pointer to some user data or NULL
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* @param channel The channel number
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* @param status Status of the transfer
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* - DMA_STATUS_COMPLETE buffer fully consumed
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* - DMA_STATUS_BLOCK buffer consumption reached a configured block
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* or water mark
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* - A negative errno otherwise
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*/
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typedef void (*dma_callback_t)(const struct device *dev, void *user_data,
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uint32_t channel, int status);
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/**
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* @struct dma_config
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* @brief DMA configuration structure.
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*/
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struct dma_config {
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/** Which peripheral and direction, HW specific */
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uint32_t dma_slot : 8;
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/**
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* Direction the transfers are occurring
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*
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* - 0b000 memory to memory,
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* - 0b001 memory to peripheral,
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* - 0b010 peripheral to memory,
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* - 0b011 peripheral to peripheral,
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* - 0b100 host to memory
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* - 0b101 memory to host
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* - others hardware specific
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*/
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uint32_t channel_direction : 3;
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/**
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* Completion callback enable
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*
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* - 0b0 callback invoked at transfer list completion only
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* - 0b1 callback invoked at completion of each block
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*/
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uint32_t complete_callback_en : 1;
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/**
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* Error callback disable
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*
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* - 0b0 error callback enabled
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* - 0b1 error callback disabled
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*/
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uint32_t error_callback_dis : 1;
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/**
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* Source handshake, HW specific
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*
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* - 0b0 HW
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* - 0b1 SW
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*/
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uint32_t source_handshake : 1;
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/**
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* Destination handshake, HW specific
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*
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* - 0b0 HW
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* - 0b1 SW
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*/
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uint32_t dest_handshake : 1;
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/**
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* Channel priority for arbitration, HW specific
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*/
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uint32_t channel_priority : 4;
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/** Source chaining enable, HW specific */
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uint32_t source_chaining_en : 1;
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/** Destination chaining enable, HW specific */
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uint32_t dest_chaining_en : 1;
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/** Linked channel, HW specific */
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uint32_t linked_channel : 7;
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/** Cyclic transfer list, HW specific */
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uint32_t cyclic : 1;
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uint32_t _reserved : 3;
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/** Width of source data (in bytes) */
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uint32_t source_data_size : 16;
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/** Width of destination data (in bytes) */
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uint32_t dest_data_size : 16;
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/** Source burst length in bytes */
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uint32_t source_burst_length : 16;
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/** Destination burst length in bytes */
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uint32_t dest_burst_length : 16;
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/** Number of blocks in transfer list */
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uint32_t block_count;
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/** Pointer to the first block in the transfer list */
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struct dma_block_config *head_block;
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/** Optional attached user data for callbacks */
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void *user_data;
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/** Optional callback for completion and error events */
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dma_callback_t dma_callback;
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};
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/**
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* DMA runtime status structure
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*/
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struct dma_status {
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/** Is the current DMA transfer busy or idle */
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bool busy;
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/** Direction fo the transfer */
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enum dma_channel_direction dir;
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/** Pending length to be transferred in bytes, HW specific */
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uint32_t pending_length;
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/** Available buffers space, HW specific */
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uint32_t free;
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/** Write position in circular DMA buffer, HW specific */
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uint32_t write_position;
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/** Read position in circular DMA buffer, HW specific */
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uint32_t read_position;
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/** Total copied, HW specific */
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uint64_t total_copied;
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};
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/**
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* DMA context structure
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* Note: the dma_context shall be the first member
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* of DMA client driver Data, got by dev->data
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*/
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struct dma_context {
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/** magic code to identify the context */
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int32_t magic;
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/** number of dma channels */
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int dma_channels;
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/** atomic holding bit flags for each channel to mark as used/unused */
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atomic_t *atomic;
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};
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/** Magic code to identify context content */
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#define DMA_MAGIC 0x47494749
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/**
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* @cond INTERNAL_HIDDEN
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*
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* These are for internal use only, so skip these in
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* public documentation.
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*/
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typedef int (*dma_api_config)(const struct device *dev, uint32_t channel,
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struct dma_config *config);
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#ifdef CONFIG_DMA_64BIT
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typedef int (*dma_api_reload)(const struct device *dev, uint32_t channel,
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uint64_t src, uint64_t dst, size_t size);
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#else
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typedef int (*dma_api_reload)(const struct device *dev, uint32_t channel,
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uint32_t src, uint32_t dst, size_t size);
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#endif
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typedef int (*dma_api_start)(const struct device *dev, uint32_t channel);
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typedef int (*dma_api_stop)(const struct device *dev, uint32_t channel);
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typedef int (*dma_api_suspend)(const struct device *dev, uint32_t channel);
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typedef int (*dma_api_resume)(const struct device *dev, uint32_t channel);
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typedef int (*dma_api_get_status)(const struct device *dev, uint32_t channel,
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struct dma_status *status);
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typedef int (*dma_api_get_attribute)(const struct device *dev, uint32_t type, uint32_t *value);
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/**
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* @typedef dma_chan_filter
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* @brief channel filter function call
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*
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* filter function that is used to find the matched internal dma channel
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* provide by caller
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*
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* @param dev Pointer to the DMA device instance
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* @param channel the channel id to use
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* @param filter_param filter function parameter, can be NULL
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*
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* @retval True on filter matched otherwise return False.
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*/
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typedef bool (*dma_api_chan_filter)(const struct device *dev,
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int channel, void *filter_param);
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__subsystem struct dma_driver_api {
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dma_api_config config;
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dma_api_reload reload;
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dma_api_start start;
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dma_api_stop stop;
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dma_api_suspend suspend;
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dma_api_resume resume;
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dma_api_get_status get_status;
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dma_api_get_attribute get_attribute;
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dma_api_chan_filter chan_filter;
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};
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/**
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* @endcond
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*/
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/**
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* @brief Configure individual channel for DMA transfer.
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel to configure
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* @param config Data structure containing the intended configuration for the
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* selected channel
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*
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* @retval 0 if successful.
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* @retval Negative errno code if failure.
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*/
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static inline int dma_config(const struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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const struct dma_driver_api *api =
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(const struct dma_driver_api *)dev->api;
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return api->config(dev, channel, config);
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}
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/**
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* @brief Reload buffer(s) for a DMA channel
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel to configure
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* selected channel
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* @param src source address for the DMA transfer
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* @param dst destination address for the DMA transfer
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* @param size size of DMA transfer
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*
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* @retval 0 if successful.
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* @retval Negative errno code if failure.
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*/
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#ifdef CONFIG_DMA_64BIT
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static inline int dma_reload(const struct device *dev, uint32_t channel,
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uint64_t src, uint64_t dst, size_t size)
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#else
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static inline int dma_reload(const struct device *dev, uint32_t channel,
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uint32_t src, uint32_t dst, size_t size)
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#endif
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{
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const struct dma_driver_api *api =
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(const struct dma_driver_api *)dev->api;
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if (api->reload) {
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return api->reload(dev, channel, src, dst, size);
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}
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return -ENOSYS;
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}
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/**
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* @brief Enables DMA channel and starts the transfer, the channel must be
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* configured beforehand.
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*
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* Implementations must check the validity of the channel ID passed in and
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* return -EINVAL if it is invalid.
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*
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* Start is allowed on channels that have already been started and must report
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* success.
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*
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* @funcprops \isr_ok
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel where the transfer will
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* be processed
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*
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* @retval 0 if successful.
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* @retval Negative errno code if failure.
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*/
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__syscall int dma_start(const struct device *dev, uint32_t channel);
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static inline int z_impl_dma_start(const struct device *dev, uint32_t channel)
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{
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const struct dma_driver_api *api =
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(const struct dma_driver_api *)dev->api;
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return api->start(dev, channel);
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}
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/**
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* @brief Stops the DMA transfer and disables the channel.
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*
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* Implementations must check the validity of the channel ID passed in and
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* return -EINVAL if it is invalid.
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*
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* Stop is allowed on channels that have already been stopped and must report
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* success.
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*
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* @funcprops \isr_ok
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel where the transfer was
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* being processed
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*
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* @retval 0 if successful.
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* @retval Negative errno code if failure.
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*/
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__syscall int dma_stop(const struct device *dev, uint32_t channel);
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static inline int z_impl_dma_stop(const struct device *dev, uint32_t channel)
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{
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const struct dma_driver_api *api =
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(const struct dma_driver_api *)dev->api;
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return api->stop(dev, channel);
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}
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/**
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* @brief Suspend a DMA channel transfer
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*
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* Implementations must check the validity of the channel state and ID passed
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* in and return -EINVAL if either are invalid.
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*
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* @funcprops \isr_ok
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel to suspend
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*
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* @retval 0 If successful.
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* @retval -ENOSYS If not implemented.
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* @retval -EINVAL If invalid channel id or state.
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* @retval -errno Other negative errno code failure.
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*/
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__syscall int dma_suspend(const struct device *dev, uint32_t channel);
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static inline int z_impl_dma_suspend(const struct device *dev, uint32_t channel)
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{
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const struct dma_driver_api *api = (const struct dma_driver_api *)dev->api;
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if (api->suspend == NULL) {
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return -ENOSYS;
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}
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return api->suspend(dev, channel);
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}
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/**
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* @brief Resume a DMA channel transfer
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*
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* Implementations must check the validity of the channel state and ID passed
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* in and return -EINVAL if either are invalid.
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*
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* @funcprops \isr_ok
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel Numeric identification of the channel to resume
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*
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* @retval 0 If successful.
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* @retval -ENOSYS If not implemented
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* @retval -EINVAL If invalid channel id or state.
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* @retval -errno Other negative errno code failure.
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*/
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__syscall int dma_resume(const struct device *dev, uint32_t channel);
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static inline int z_impl_dma_resume(const struct device *dev, uint32_t channel)
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{
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const struct dma_driver_api *api = (const struct dma_driver_api *)dev->api;
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if (api->resume == NULL) {
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return -ENOSYS;
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}
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return api->resume(dev, channel);
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}
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/**
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* @brief request DMA channel.
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*
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* request DMA channel resources
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* return -EINVAL if there is no valid channel available.
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*
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* @funcprops \isr_ok
|
|
*
|
|
* @param dev Pointer to the device structure for the driver instance.
|
|
* @param filter_param filter function parameter
|
|
*
|
|
* @retval dma channel if successful.
|
|
* @retval Negative errno code if failure.
|
|
*/
|
|
__syscall int dma_request_channel(const struct device *dev,
|
|
void *filter_param);
|
|
|
|
static inline int z_impl_dma_request_channel(const struct device *dev,
|
|
void *filter_param)
|
|
{
|
|
int i = 0;
|
|
int channel = -EINVAL;
|
|
const struct dma_driver_api *api =
|
|
(const struct dma_driver_api *)dev->api;
|
|
/* dma_context shall be the first one in dev data */
|
|
struct dma_context *dma_ctx = (struct dma_context *)dev->data;
|
|
|
|
if (dma_ctx->magic != DMA_MAGIC) {
|
|
return channel;
|
|
}
|
|
|
|
for (i = 0; i < dma_ctx->dma_channels; i++) {
|
|
if (!atomic_test_and_set_bit(dma_ctx->atomic, i)) {
|
|
if (api->chan_filter &&
|
|
!api->chan_filter(dev, i, filter_param)) {
|
|
atomic_clear_bit(dma_ctx->atomic, i);
|
|
continue;
|
|
}
|
|
channel = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return channel;
|
|
}
|
|
|
|
/**
|
|
* @brief release DMA channel.
|
|
*
|
|
* release DMA channel resources
|
|
*
|
|
* @funcprops \isr_ok
|
|
*
|
|
* @param dev Pointer to the device structure for the driver instance.
|
|
* @param channel channel number
|
|
*
|
|
*/
|
|
__syscall void dma_release_channel(const struct device *dev,
|
|
uint32_t channel);
|
|
|
|
static inline void z_impl_dma_release_channel(const struct device *dev,
|
|
uint32_t channel)
|
|
{
|
|
struct dma_context *dma_ctx = (struct dma_context *)dev->data;
|
|
|
|
if (dma_ctx->magic != DMA_MAGIC) {
|
|
return;
|
|
}
|
|
|
|
if ((int)channel < dma_ctx->dma_channels) {
|
|
atomic_clear_bit(dma_ctx->atomic, channel);
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief DMA channel filter.
|
|
*
|
|
* filter channel by attribute
|
|
*
|
|
* @param dev Pointer to the device structure for the driver instance.
|
|
* @param channel channel number
|
|
* @param filter_param filter attribute
|
|
*
|
|
* @retval Negative errno code if not support
|
|
*
|
|
*/
|
|
__syscall int dma_chan_filter(const struct device *dev,
|
|
int channel, void *filter_param);
|
|
|
|
static inline int z_impl_dma_chan_filter(const struct device *dev,
|
|
int channel, void *filter_param)
|
|
{
|
|
const struct dma_driver_api *api =
|
|
(const struct dma_driver_api *)dev->api;
|
|
|
|
if (api->chan_filter) {
|
|
return api->chan_filter(dev, channel, filter_param);
|
|
}
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* @brief get current runtime status of DMA transfer
|
|
*
|
|
* Implementations must check the validity of the channel ID passed in and
|
|
* return -EINVAL if it is invalid or -ENOSYS if not supported.
|
|
*
|
|
* @funcprops \isr_ok
|
|
*
|
|
* @param dev Pointer to the device structure for the driver instance.
|
|
* @param channel Numeric identification of the channel where the transfer was
|
|
* being processed
|
|
* @param stat a non-NULL dma_status object for storing DMA status
|
|
*
|
|
* @retval non-negative if successful.
|
|
* @retval Negative errno code if failure.
|
|
*/
|
|
static inline int dma_get_status(const struct device *dev, uint32_t channel,
|
|
struct dma_status *stat)
|
|
{
|
|
const struct dma_driver_api *api =
|
|
(const struct dma_driver_api *)dev->api;
|
|
|
|
if (api->get_status) {
|
|
return api->get_status(dev, channel, stat);
|
|
}
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* @brief get attribute of a dma controller
|
|
*
|
|
* This function allows to get a device specific static or runtime attribute like required address
|
|
* and size alignment of a buffer.
|
|
* Implementations must check the validity of the type passed in and
|
|
* return -EINVAL if it is invalid or -ENOSYS if not supported.
|
|
*
|
|
* @funcprops \isr_ok
|
|
*
|
|
* @param dev Pointer to the device structure for the driver instance.
|
|
* @param type Numeric identification of the attribute
|
|
* @param value A non-NULL pointer to the variable where the read value is to be placed
|
|
*
|
|
* @retval non-negative if successful.
|
|
* @retval Negative errno code if failure.
|
|
*/
|
|
static inline int dma_get_attribute(const struct device *dev, uint32_t type, uint32_t *value)
|
|
{
|
|
const struct dma_driver_api *api = (const struct dma_driver_api *)dev->api;
|
|
|
|
if (api->get_attribute) {
|
|
return api->get_attribute(dev, type, value);
|
|
}
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/**
|
|
* @brief Look-up generic width index to be used in registers
|
|
*
|
|
* @warning This look-up works for most controllers, but *may* not work for
|
|
* yours. Ensure your controller expects the most common register
|
|
* bit values before using this convenience function. If your
|
|
* controller does not support these values, you will have to write
|
|
* your own look-up inside the controller driver.
|
|
*
|
|
* @param size: width of bus (in bytes)
|
|
*
|
|
* @retval common DMA index to be placed into registers.
|
|
*/
|
|
static inline uint32_t dma_width_index(uint32_t size)
|
|
{
|
|
/* Check boundaries (max supported width is 32 Bytes) */
|
|
if (size < 1 || size > 32) {
|
|
return 0; /* Zero is the default (8 Bytes) */
|
|
}
|
|
|
|
/* Ensure size is a power of 2 */
|
|
if (!is_power_of_two(size)) {
|
|
return 0; /* Zero is the default (8 Bytes) */
|
|
}
|
|
|
|
/* Convert to bit pattern for writing to a register */
|
|
return find_msb_set(size);
|
|
}
|
|
|
|
/**
|
|
* @brief Look-up generic burst index to be used in registers
|
|
*
|
|
* @warning This look-up works for most controllers, but *may* not work for
|
|
* yours. Ensure your controller expects the most common register
|
|
* bit values before using this convenience function. If your
|
|
* controller does not support these values, you will have to write
|
|
* your own look-up inside the controller driver.
|
|
*
|
|
* @param burst: number of bytes to be sent in a single burst
|
|
*
|
|
* @retval common DMA index to be placed into registers.
|
|
*/
|
|
static inline uint32_t dma_burst_index(uint32_t burst)
|
|
{
|
|
/* Check boundaries (max supported burst length is 256) */
|
|
if (burst < 1 || burst > 256) {
|
|
return 0; /* Zero is the default (1 burst length) */
|
|
}
|
|
|
|
/* Ensure burst is a power of 2 */
|
|
if (!(burst & (burst - 1))) {
|
|
return 0; /* Zero is the default (1 burst length) */
|
|
}
|
|
|
|
/* Convert to bit pattern for writing to a register */
|
|
return find_msb_set(burst);
|
|
}
|
|
|
|
/**
|
|
* @brief Get the device tree property describing the buffer address alignment
|
|
*
|
|
* Useful when statically defining or allocating buffers for DMA usage where
|
|
* memory alignment often matters.
|
|
*
|
|
* @param node Node identifier, e.g. DT_NODELABEL(dma_0)
|
|
* @return alignment Memory byte alignment required for DMA buffers
|
|
*/
|
|
#define DMA_BUF_ADDR_ALIGNMENT(node) DT_PROP(node, dma_buf_addr_alignment)
|
|
|
|
/**
|
|
* @brief Get the device tree property describing the buffer size alignment
|
|
*
|
|
* Useful when statically defining or allocating buffers for DMA usage where
|
|
* memory alignment often matters.
|
|
*
|
|
* @param node Node identifier, e.g. DT_NODELABEL(dma_0)
|
|
* @return alignment Memory byte alignment required for DMA buffers
|
|
*/
|
|
#define DMA_BUF_SIZE_ALIGNMENT(node) DT_PROP(node, dma_buf_size_alignment)
|
|
|
|
/**
|
|
* @brief Get the device tree property describing the minimal chunk of data possible to be copied
|
|
*
|
|
* @param node Node identifier, e.g. DT_NODELABEL(dma_0)
|
|
* @return minimal Minimal chunk of data possible to be copied
|
|
*/
|
|
#define DMA_COPY_ALIGNMENT(node) DT_PROP(node, dma_copy_alignment)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#include <zephyr/syscalls/dma.h>
|
|
|
|
#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_H_ */
|