d796c117ce
The clk, dqs and ncs pins can be remapped between OSPI instances, but the driver doesn't support it, yet. Therefore replace hard coded numbers to device tree optional properties. Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
167 lines
4.6 KiB
YAML
167 lines
4.6 KiB
YAML
# Copyright (c) 2022 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 OSPI device representation. Enabling a stm32 octospi node in a board
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description would typically requires this:
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&octospi {
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pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
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&octospi_io0_pe12 &octospi_io1_pe13
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&octospi_io2_pe14 &octospi_io3_pe15
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&octospi_io4_pe16 &octospi_io5_pe17
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&octospi_io6_pe18 &octospi_io7_pe19>;
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dmas = <&dma1 5 41 0x10000>;
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dma-names = "tx_rx";
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status = "okay";
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};
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compatible: "st,stm32-ospi"
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include: [base.yaml, pinctrl-device.yaml]
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bus: ospi
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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clock-names:
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required: true
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dmas:
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description: |
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Optional DMA channel specifier, required for DMA transactions.
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For example dmas for TX/RX on OSPI
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dmas = <&dma1 5 41 0x10000>;
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With, in each cell of the dmas specifier:
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- &dma1: dma controller phandle
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- 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
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- 41: slot number (request which could be given by the DMAMUX)
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- 0x10000: channel configuration (only for srce/dest data size, priority)
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Notes:
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- On series supporting DMAMUX, the DMA phandle should be provided
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but DMAMUX node should also be enabled in the DTS.
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- For channel configuration, only the config bits priority and
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periph/mem datasize are used. The periph/mem datasize must be equal,
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0 is a correct value.
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- There is no Fifo used by this DMA peripheral.
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For example dmas for TX/RX on OSPI
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dmas = <&dma1 5 41 0x10000>;
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dma-names:
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description: |
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DMA channel name. If DMA should be used, expected value is "tx_rx".
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For example
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dma-names = "tx_rx";
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dlyb-bypass:
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type: boolean
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description: |
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Enables Delay Block (DLYB) Bypass.
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ssht-enable:
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type: boolean
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description: |
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Enables Sample Shifting half-cycle.
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It is recommended to be enabled in STR mode and disabled in DTR mode.
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io-low-port:
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type: string
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enum:
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- "IOPORT_NONE"
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- "IOPORT_1_LOW"
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- "IOPORT_1_HIGH"
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- "IOPORT_2_LOW"
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- "IOPORT_2_HIGH"
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the IO[3:0] pins.
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If absent, then `IOPORT_<n>_LOW` is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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io-high-port:
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type: string
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enum:
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- "IOPORT_NONE"
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- "IOPORT_1_LOW"
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- "IOPORT_1_HIGH"
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- "IOPORT_2_LOW"
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- "IOPORT_2_HIGH"
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the IO[7:4] pins.
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If absent, then `IOPORT_<n>_HIGH` is used where `n` is the OSPI
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instance number.
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Can be set to `IOPORT_NONE` for Single SPI, Dual SPI and Quad SPI.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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clk-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the clk pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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dqs-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the dqs pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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ncs-port:
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type: int
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enum:
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- 1
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- 2
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description: |
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Specifies which port of the OCTOSPI IO Manager is used for the ncs pin.
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If absent, then n is used where `n` is the OSPI
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instance number.
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Note: You might need to enable the OCTOSPI I/O manager clock to use the
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property. Please refer to Reference Manual.
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The clock can be enabled in the devicetree.
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