671d857a60
SIUL2 may require multiple interrupt handlers instead of a single one as currently supported for S32Z/E. This is needed to enable support on S32K3. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
72 lines
1.8 KiB
YAML
72 lines
1.8 KiB
YAML
# Copyright 2022-2023 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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description: NXP S32 SIUL2 External Interrupts Request controller
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compatible: "nxp,s32-siul2-eirq"
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include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
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properties:
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reg:
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required: true
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reg-names:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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filter-prescaler:
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type: int
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description: |
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Setting the prescaler which selects the clock for all digital filters.
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Valid range: 0 - 15.
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interrupt-names:
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description: |
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For platforms that external interrupt lines belong to different interrupt
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IDs (i.e. there is no single interrupt handler for all the lines), this
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property is used by the shim driver to determine the ISR name as defined
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by the HAL.
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The naming must follow: <from-line-number>_<to-line-number>, for example:
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interrupt-names = "0_7", "8_15", "16_23", "24_31";
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child-binding:
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description: |
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NXP S32 SIUL2 External Interrupt line configuration. For each
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interrupt line that has specific requirements about digital
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glitch filter, a node using this binding must be added, the
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name must be "line_<line_number>". For example:
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line_0: line_0 {
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filter-enable;
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filter-counter = <5>;
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};
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If the controller has no child node, the digital filter will be
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disabled for all external interrupt lines.
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properties:
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filter-enable:
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type: boolean
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required: true
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description: |
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Enable digital glitch filter to filter out glitches on the input pad.
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filter-counter:
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type: int
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required: true
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description: |
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Configuring the filter counter associated with digital glitch filter.
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Valid range: 0 - 15.
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interrupt-cells:
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- gpio-pin
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- eirq-line
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