13a87081b9
MEC172X series SoCs share most IP but the -LJ series expands the PWM and ADC channels available as well as defines extra pinctrl pins. Separating these better to be able to simplify their inclusion and driver code. Any board based on either the -SZ or -LJ package can just include the mec172x<sz/lj> dtsi files for their specific package. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2021 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
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#include <freq.h>
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#include <mem.h>
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#include "mec172x/mec172x-vw-routing.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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cpu-power-states = <&idle &suspend_to_ram>;
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};
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power-states {
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <1000000>;
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};
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suspend_to_ram: suspend_to_ram {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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min-residency-us = <2000000>;
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};
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};
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};
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flash0: flash@c0000 {
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reg = <0x000C0000 0x58000>;
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};
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sram0: memory@118000 {
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compatible = "mmio-sram";
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reg = <0x00118000 0x10000>;
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};
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soc {
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#include "mec172x_common.dtsi"
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eeprom: eeprom@40002c00 {
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compatible = "microchip,xec-eeprom";
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reg = <0x40002c00 0x400>;
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interrupts = <155 2>;
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size = <2048>;
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girqs = <18 13>;
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pcrs = <4 14>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&systick {
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status = "disabled";
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};
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