6639756fae
This is Intel's proprietary IP which controls individual module reset signals. During each system driver initialization, these reset signals will be used to bring module out of reset state. Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com> Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_socfpga_reset
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#include <zephyr/device.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/kernel.h>
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/** regwidth 4 for 32 bit register */
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#define RESET_REG_WIDTH 4
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struct reset_intel_config {
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DEVICE_MMIO_ROM;
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/* check peripheral active low / active high */
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bool active_low;
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};
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struct reset_intel_soc_data {
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DEVICE_MMIO_RAM;
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};
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static int32_t reset_intel_soc_status(const struct device *dev, uint32_t id, uint8_t *status)
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{
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const struct reset_intel_config *config = (const struct reset_intel_config *)dev->config;
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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uint32_t value;
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uint16_t offset;
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uint8_t regbit;
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regbit = (id & ((RESET_REG_WIDTH << (RESET_REG_WIDTH - 1)) - 1));
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offset = (id >> (RESET_REG_WIDTH + 1)) << (RESET_REG_WIDTH >> 1);
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value = sys_read32(base_address + offset);
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*status = !(value & BIT(regbit)) ^ config->active_low;
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return 0;
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}
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static void reset_intel_soc_update(const struct device *dev, uint32_t id, bool assert)
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{
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const struct reset_intel_config *config = (const struct reset_intel_config *)dev->config;
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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uint16_t offset;
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uint8_t regbit;
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regbit = (id & ((RESET_REG_WIDTH << (RESET_REG_WIDTH - 1)) - 1));
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offset = (id >> (RESET_REG_WIDTH + 1)) << (RESET_REG_WIDTH >> 1);
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if (assert ^ !config->active_low) {
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if (sys_test_bit(base_address + offset, regbit) == 0) {
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sys_set_bit(base_address + offset, regbit);
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}
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} else {
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if (sys_test_bit(base_address + offset, regbit) != 0) {
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sys_clear_bit(base_address + offset, regbit);
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}
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}
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}
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static int32_t reset_intel_soc_line_assert(const struct device *dev, uint32_t id)
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{
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reset_intel_soc_update(dev, id, true);
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return 0;
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}
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static int32_t reset_intel_soc_line_deassert(const struct device *dev, uint32_t id)
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{
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reset_intel_soc_update(dev, id, false);
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return 0;
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}
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static int32_t reset_intel_soc_line_toggle(const struct device *dev, uint32_t id)
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{
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(void)reset_intel_soc_line_assert(dev, id);
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/* TODO: Add required delay once tested on Emulator/Hardware platform. */
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(void)reset_intel_soc_line_deassert(dev, id);
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return 0;
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}
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static int32_t reset_intel_soc_init(const struct device *dev)
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{
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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return 0;
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}
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static const struct reset_driver_api reset_intel_soc_driver_api = {
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.status = reset_intel_soc_status,
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.line_assert = reset_intel_soc_line_assert,
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.line_deassert = reset_intel_soc_line_deassert,
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.line_toggle = reset_intel_soc_line_toggle,
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};
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#define INTEL_SOC_RESET_INIT(_inst) \
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static struct reset_intel_soc_data reset_intel_soc_data_##_inst; \
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static const struct reset_intel_config reset_intel_config_##_inst = { \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(_inst)), \
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.active_low = DT_INST_PROP(_inst, active_low), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(_inst, \
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reset_intel_soc_init, \
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NULL, \
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&reset_intel_soc_data_##_inst, \
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&reset_intel_config_##_inst, \
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PRE_KERNEL_1, \
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CONFIG_RESET_INIT_PRIORITY, \
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&reset_intel_soc_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_SOC_RESET_INIT);
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