ef8b8a2983
Do not reset the FLEXSPI during init, as this will crash the chip if we are running the MEMC driver in XIP mode. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
248 lines
7.3 KiB
C
248 lines
7.3 KiB
C
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_is66wvq8m4
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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#include "memc_mcux_flexspi.h"
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LOG_MODULE_REGISTER(memc_flexspi_is66wvq8m4, CONFIG_MEMC_LOG_LEVEL);
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/* Vendor ID for ISSI device */
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#define ISSI_VENDOR_ID 0x3
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enum {
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READ_DATA = 0,
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WRITE_DATA,
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READ_REG,
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WRITE_REG,
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READ_ID,
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};
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struct memc_flexspi_is66wvq8m4_config {
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flexspi_port_t port;
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flexspi_device_config_t config;
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};
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/* Device variables used in critical sections should be in this structure */
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struct memc_flexspi_is66wvq8m4_data {
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const struct device *controller;
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};
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/* IS66WVQ8M4 configuration register constants */
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#define IS66WVQ8M4_LATENCY_MASK BIT(3)
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#define IS66WVQ8M4_LATENCY_FIXED BIT(3)
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static const uint32_t memc_flexspi_is66wvq8m4_lut[][4] = {
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/* Read Data (continuous burst) */
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[READ_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0xAA,
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kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x00),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16,
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD, 16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_4PAD, 28,
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kFLEXSPI_Command_READ_DDR, kFLEXSPI_4PAD, 0x01),
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},
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/* Write Data (continuous burst) */
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[WRITE_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x22,
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kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x00),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16,
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD, 16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_4PAD, 28,
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_4PAD, 0x01),
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},
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/* Read Register */
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[READ_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0xCC,
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kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x00),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16,
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD, 16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_4PAD, 12,
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kFLEXSPI_Command_READ_DDR, kFLEXSPI_4PAD, 0x01),
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},
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/* Write Register */
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[WRITE_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x66,
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kFLEXSPI_Command_DDR, kFLEXSPI_4PAD, 0x00),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16,
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD, 16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_4PAD, 0x01,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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/* Read Identification register */
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[READ_ID] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xE0,
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kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_4PAD, 16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_4PAD, 16,
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kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_4PAD, 0x08),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_4PAD, 0x01,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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}
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};
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/* Read vendor ID from identification register */
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static int memc_flexspi_is66wvq8m4_get_vendor_id(const struct device *dev,
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uint8_t *vendor_id)
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{
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const struct memc_flexspi_is66wvq8m4_config *config = dev->config;
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struct memc_flexspi_is66wvq8m4_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0x00, /* Not used by this command */
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_ID,
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.data = &buffer,
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.dataSize = 2,
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};
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ret = memc_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer & 0x7;
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return ret;
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}
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/* Update configuration register */
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static int memc_flexspi_is66wvq8m4_update_cfg(const struct device *dev,
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uint16_t mask, uint16_t set_val)
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{
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const struct memc_flexspi_is66wvq8m4_config *config = dev->config;
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struct memc_flexspi_is66wvq8m4_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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/* Results in 0x4 being written on clock 4 */
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.deviceAddress = (0x4 << 9),
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_REG,
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.data = &buffer,
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.dataSize = 2,
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};
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret < 0) {
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return ret;
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}
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buffer &= (~mask & GENMASK(15, 0));
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buffer |= set_val;
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LOG_DBG("Setting cfg reg to 0x%0x", buffer);
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transfer.cmdType = kFLEXSPI_Write,
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transfer.seqIndex = WRITE_REG;
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ret = memc_flexspi_transfer(data->controller, &transfer);
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return ret;
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}
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static int memc_flexspi_is66wvq8m4_init(const struct device *dev)
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{
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const struct memc_flexspi_is66wvq8m4_config *config = dev->config;
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struct memc_flexspi_is66wvq8m4_data *data = dev->data;
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uint8_t vendor_id;
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if (!device_is_ready(data->controller)) {
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LOG_ERR("Controller device not ready");
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return -ENODEV;
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}
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if (memc_flexspi_set_device_config(data->controller, &config->config,
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(const uint32_t *) memc_flexspi_is66wvq8m4_lut,
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sizeof(memc_flexspi_is66wvq8m4_lut) / MEMC_FLEXSPI_CMD_SIZE,
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config->port)) {
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LOG_ERR("Could not set device configuration");
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return -EINVAL;
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}
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if (memc_flexspi_is66wvq8m4_get_vendor_id(dev, &vendor_id)) {
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LOG_ERR("Could not read vendor id");
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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if (vendor_id != ISSI_VENDOR_ID) {
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LOG_WRN("Vendor ID does not match expected value of 0x%0x",
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ISSI_VENDOR_ID);
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}
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if (memc_flexspi_is66wvq8m4_update_cfg(dev, IS66WVQ8M4_LATENCY_MASK,
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IS66WVQ8M4_LATENCY_FIXED)) {
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LOG_ERR("Could not set fixed latency mode");
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return -EIO;
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}
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return 0;
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}
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#define CONCAT3(x, y, z) x ## y ## z
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#define CS_INTERVAL_UNIT(unit) \
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CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
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#define AHB_WRITE_WAIT_UNIT(unit) \
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CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
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#define MEMC_FLEXSPI_DEVICE_CONFIG(n) \
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{ \
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.flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
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.isSck2Enabled = false, \
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.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
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.addressShift = DT_INST_REG_ADDR(n) != 0, \
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.CSIntervalUnit = \
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CS_INTERVAL_UNIT( \
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DT_INST_PROP(n, cs_interval_unit)), \
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.CSInterval = DT_INST_PROP(n, cs_interval), \
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.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
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.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
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.dataValidTime = DT_INST_PROP(n, data_valid_time), \
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.columnspace = DT_INST_PROP(n, column_space), \
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.enableWordAddress = DT_INST_PROP(n, word_addressable), \
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.AWRSeqIndex = WRITE_DATA, \
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.AWRSeqNumber = 1, \
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.ARDSeqIndex = READ_DATA, \
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.ARDSeqNumber = 1, \
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.AHBWriteWaitUnit = \
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AHB_WRITE_WAIT_UNIT( \
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DT_INST_PROP(n, ahb_write_wait_unit)), \
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.AHBWriteWaitInterval = \
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DT_INST_PROP(n, ahb_write_wait_interval), \
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.enableWriteMask = true, \
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}
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#define MEMC_FLEXSPI_IS66WVQ8M4(n) \
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static const struct memc_flexspi_is66wvq8m4_config \
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memc_flexspi_is66wvq8m4_config_##n = { \
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.port = DT_INST_REG_ADDR(n), \
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.config = MEMC_FLEXSPI_DEVICE_CONFIG(n), \
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}; \
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\
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static struct memc_flexspi_is66wvq8m4_data \
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memc_flexspi_is66wvq8m4_data_##n = { \
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.controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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memc_flexspi_is66wvq8m4_init, \
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NULL, \
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&memc_flexspi_is66wvq8m4_data_##n, \
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&memc_flexspi_is66wvq8m4_config_##n,\
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POST_KERNEL, \
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CONFIG_MEMC_INIT_PRIORITY, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_IS66WVQ8M4)
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