386 lines
13 KiB
C
386 lines
13 KiB
C
/*
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* Copyright (c) 2023 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <string.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/irq.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/sys/atomic.h>
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#include <zephyr/sys/barrier.h>
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LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
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#define DT_DRV_COMPAT microchip_mpfs_i2c
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#define CORE_I2C_CTRL (0x00)
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#define CORE_I2C_STATUS (0x04)
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#define CORE_I2C_DATA (0x08)
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#define CORE_I2C_ADDR_0 (0x0C)
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#define CORE_I2C_FREQ (0x14)
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#define CORE_I2C_GLITCHREG (0x18)
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#define CORE_I2C_ADDR_1 (0x1C)
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#define CTRL_CR0 BIT(0)
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#define CTRL_CR1 BIT(1)
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#define CTRL_AA BIT(2)
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#define CTRL_SI BIT(3)
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#define CTRL_STO BIT(4)
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#define CTRL_STA BIT(5)
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#define CTRL_ENS1 BIT(6)
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#define CTRL_CR2 BIT(7)
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#define STATUS_M_START_SENT (0x08)
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#define STATUS_M_REPEATED_START_SENT (0x10)
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#define STATUS_M_SLAW_ACK (0x18)
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#define STATUS_M_SLAW_NACK (0x20)
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#define STATUS_M_TX_DATA_ACK (0x28)
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#define STATUS_M_TX_DATA_NACK (0x30)
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#define STATUS_M_ARB_LOST (0x38)
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#define STATUS_M_SLAR_ACK (0x40)
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#define STATUS_M_SLAR_NACK (0x48)
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#define STATUS_M_RX_DATA_ACKED (0x50)
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#define STATUS_M_RX_DATA_NACKED (0x58)
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#define STATUS_S_SLAW_ACKED (0x60)
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#define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
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#define STATUS_S_GENERAL_CALL_ACKED (0x70)
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#define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
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#define STATUS_S_RX_DATA_ACKED (0x80)
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#define STATUS_S_RX_DATA_NACKED (0x88)
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#define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
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#define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
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#define STATUS_S_RX_STOP (0xA0)
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#define STATUS_S_SLAR_ACKED (0xA8)
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#define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
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#define STATUS_S_TX_DATA_ACK (0xB8)
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#define STATUS_S_TX_DATA_NACK (0xC0)
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#define STATUS_LAST_DATA_ACK (0xC8)
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#define PCLK_DIV_960 (CTRL_CR2)
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#define PCLK_DIV_256 (0)
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#define PCLK_DIV_224 (CTRL_CR0)
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#define PCLK_DIV_192 (CTRL_CR1)
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#define PCLK_DIV_160 (CTRL_CR0 | CTRL_CR1)
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#define PCLK_DIV_120 (CTRL_CR0 | CTRL_CR2)
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#define PCLK_DIV_60 (CTRL_CR1 | CTRL_CR2)
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#define BCLK_DIV_8 (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
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#define CLK_MASK (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
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/* -- Transactions types -- */
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#define NO_TRANSACTION (0x00)
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#define CONTROLLER_WRITE_TRANSACTION (0x01)
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#define CONTROLLER_READ_TRANSACTION (0x02)
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#define CONTROLLER_RANDOM_READ_TRANSACTION (0x03)
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#define WRITE_TARGET_TRANSACTION (0x04)
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#define READ_TARGET_TRANSACTION (0x05)
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#define MSS_I2C_RELEASE_BUS (0x00)
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#define MSS_I2C_HOLD_BUS (0x01)
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#define TARGET_ADDR_SHIFT (0x01)
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#define MSS_I2C_SUCCESS (0x00)
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#define MSS_I2C_IN_PROGRESS (0x01)
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#define MSS_I2C_FAILED (0x02)
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#define MSS_I2C_TIMED_OUT (0x03)
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struct mss_i2c_config {
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uint32_t clock_freq;
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uintptr_t i2c_base_addr;
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uint32_t i2c_irq_base;
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};
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struct mss_i2c_data {
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uint8_t ser_address;
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uint8_t target_addr;
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uint8_t options;
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uint8_t transaction;
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const uint8_t *controller_tx_buffer;
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uint16_t controller_tx_size;
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uint16_t controller_tx_idx;
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uint8_t dir;
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uint8_t *controller_rx_buffer;
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uint16_t controller_rx_size;
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uint16_t controller_rx_idx;
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atomic_t controller_status;
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uint32_t controller_timeout_ms;
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const uint8_t *target_tx_buffer;
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uint16_t target_tx_size;
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uint16_t target_tx_idx;
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uint8_t *target_rx_buffer;
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uint16_t target_rx_size;
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uint16_t target_rx_idx;
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atomic_t target_status;
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uint8_t target_mem_offset_length;
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uint8_t is_target_enabled;
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uint8_t bus_status;
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uint8_t is_transaction_pending;
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uint8_t pending_transaction;
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sys_slist_t cb;
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};
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static int mss_i2c_configure(const struct device *dev, uint32_t dev_config_raw)
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{
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const struct mss_i2c_config *cfg = dev->config;
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uint8_t ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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switch (I2C_SPEED_GET(dev_config_raw)) {
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case I2C_SPEED_STANDARD:
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sys_write8((ctrl | PCLK_DIV_960), cfg->i2c_base_addr + CORE_I2C_CTRL);
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break;
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case I2C_SPEED_FAST:
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sys_write8((ctrl | PCLK_DIV_256), cfg->i2c_base_addr + CORE_I2C_CTRL);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mss_wait_complete(const struct device *dev)
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{
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struct mss_i2c_data *const data = dev->data;
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atomic_t i2c_status = 0;
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do {
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i2c_status = atomic_get(&data->controller_status);
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} while (i2c_status == MSS_I2C_IN_PROGRESS);
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return i2c_status;
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}
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static int mss_i2c_read(const struct device *dev, uint8_t serial_addr, uint8_t *read_buffer,
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uint32_t read_size)
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{
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struct mss_i2c_data *const data = dev->data;
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const struct mss_i2c_config *cfg = dev->config;
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uint8_t ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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data->target_addr = serial_addr << TARGET_ADDR_SHIFT;
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data->pending_transaction = CONTROLLER_READ_TRANSACTION;
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data->dir = I2C_MSG_READ;
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data->controller_rx_buffer = read_buffer;
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data->controller_rx_size = read_size;
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data->controller_rx_idx = 0u;
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sys_write8((ctrl | CTRL_STA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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return 0;
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}
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static int mss_i2c_write(const struct device *dev, uint8_t serial_addr, uint8_t *tx_buffer,
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uint32_t tx_num_write)
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{
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struct mss_i2c_data *const data = dev->data;
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const struct mss_i2c_config *cfg = dev->config;
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uint8_t ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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atomic_t target_status = data->target_status;
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if (data->transaction == NO_TRANSACTION) {
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data->transaction = CONTROLLER_WRITE_TRANSACTION;
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}
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data->pending_transaction = CONTROLLER_WRITE_TRANSACTION;
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data->target_addr = serial_addr << TARGET_ADDR_SHIFT;
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data->dir = I2C_MSG_WRITE;
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data->controller_tx_buffer = tx_buffer;
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data->controller_tx_size = tx_num_write;
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data->controller_tx_idx = 0u;
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atomic_set(&data->controller_status, MSS_I2C_IN_PROGRESS);
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if (target_status == MSS_I2C_IN_PROGRESS) {
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data->is_transaction_pending = CONTROLLER_WRITE_TRANSACTION;
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} else {
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sys_write8((ctrl | CTRL_STA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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if (data->bus_status == MSS_I2C_HOLD_BUS) {
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sys_write8((ctrl & ~CTRL_SI), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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return 0;
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}
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static int mss_i2c_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
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uint16_t addr)
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{
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for (int i = 0; i < num_msgs; i++) {
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struct i2c_msg *current = &msgs[i];
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if ((current->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
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mss_i2c_read(dev, addr, current->buf, current->len);
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mss_wait_complete(dev);
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} else {
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mss_i2c_write(dev, addr, current->buf, current->len);
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mss_wait_complete(dev);
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}
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}
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return 0;
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}
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static const struct i2c_driver_api mss_i2c_driver_api = {
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.configure = mss_i2c_configure,
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.transfer = mss_i2c_transfer,
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};
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static void mss_i2c_reset(const struct device *dev)
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{
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const struct mss_i2c_config *cfg = dev->config;
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uint8_t ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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sys_write8((ctrl & ~CTRL_ENS1), cfg->i2c_base_addr + CORE_I2C_CTRL);
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ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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sys_write8((ctrl | CTRL_ENS1), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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static void mss_i2c_irq_handler(const struct device *dev)
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{
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struct mss_i2c_data *const data = dev->data;
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const struct mss_i2c_config *cfg = dev->config;
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uint8_t ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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uint8_t status = sys_read8(cfg->i2c_base_addr + CORE_I2C_STATUS);
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uint8_t hold_bus = 0;
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switch (status) {
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case STATUS_M_START_SENT:
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case STATUS_M_REPEATED_START_SENT:
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sys_write8((ctrl & ~CTRL_STA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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sys_write8(data->target_addr | data->dir, cfg->i2c_base_addr + CORE_I2C_DATA);
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data->controller_tx_idx = 0;
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data->controller_rx_idx = 0;
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data->is_transaction_pending = false;
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data->transaction = data->pending_transaction;
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break;
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case STATUS_M_ARB_LOST:
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sys_write8((ctrl | CTRL_STA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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LOG_WRN("lost arbitration: %x\n", status);
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break;
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case STATUS_M_SLAW_ACK:
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case STATUS_M_TX_DATA_ACK:
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if (data->controller_tx_idx < data->controller_tx_size) {
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sys_write8(data->controller_tx_buffer[data->controller_tx_idx],
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cfg->i2c_base_addr + CORE_I2C_DATA);
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data->controller_tx_idx++;
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} else if (data->transaction == CONTROLLER_RANDOM_READ_TRANSACTION) {
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data->dir = I2C_MSG_READ;
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sys_write8((ctrl | CTRL_STA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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} else {
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data->transaction = NO_TRANSACTION;
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hold_bus = data->options & MSS_I2C_HOLD_BUS;
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data->bus_status = hold_bus;
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if (hold_bus == MSS_I2C_RELEASE_BUS) {
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sys_write8((ctrl | CTRL_STO), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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}
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atomic_set(&data->controller_status, MSS_I2C_SUCCESS);
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break;
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case STATUS_M_TX_DATA_NACK:
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case STATUS_M_SLAR_NACK:
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case STATUS_M_SLAW_NACK:
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sys_write8((ctrl | CTRL_STO), cfg->i2c_base_addr + CORE_I2C_CTRL);
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atomic_set(&data->controller_status, MSS_I2C_FAILED);
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data->transaction = NO_TRANSACTION;
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break;
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case STATUS_M_SLAR_ACK:
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if (data->controller_rx_size > 1u) {
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sys_write8((ctrl | CTRL_AA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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} else if (data->controller_rx_size == 1u) {
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sys_write8((ctrl & ~CTRL_AA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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} else {
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sys_write8((ctrl | CTRL_AA | CTRL_STO), cfg->i2c_base_addr + CORE_I2C_CTRL);
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atomic_set(&data->controller_status, MSS_I2C_SUCCESS);
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data->transaction = NO_TRANSACTION;
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}
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break;
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case STATUS_M_RX_DATA_ACKED:
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data->controller_rx_buffer[data->controller_rx_idx] =
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sys_read8(cfg->i2c_base_addr + CORE_I2C_DATA);
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data->controller_rx_idx++;
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/* Second Last byte */
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if (data->controller_rx_idx >= (data->controller_rx_size - 1u)) {
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sys_write8((ctrl & ~CTRL_AA), cfg->i2c_base_addr + CORE_I2C_CTRL);
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} else {
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atomic_set(&data->controller_status, MSS_I2C_IN_PROGRESS);
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}
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break;
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case STATUS_M_RX_DATA_NACKED:
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data->controller_rx_buffer[data->controller_rx_idx] =
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sys_read8(cfg->i2c_base_addr + CORE_I2C_DATA);
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hold_bus = data->options & MSS_I2C_HOLD_BUS;
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data->bus_status = hold_bus;
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if (hold_bus == 0u) {
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sys_write8((ctrl | CTRL_STO), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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data->transaction = NO_TRANSACTION;
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atomic_set(&data->controller_status, MSS_I2C_SUCCESS);
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break;
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default:
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break;
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}
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ctrl = sys_read8(cfg->i2c_base_addr + CORE_I2C_CTRL);
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sys_write8((ctrl & ~CTRL_SI), cfg->i2c_base_addr + CORE_I2C_CTRL);
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}
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#define MSS_I2C_INIT(n) \
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static int mss_i2c_init_##n(const struct device *dev) \
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{ \
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mss_i2c_reset(dev); \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mss_i2c_irq_handler, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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\
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return 0; \
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} \
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\
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static struct mss_i2c_data mss_i2c_data_##n; \
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\
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static const struct mss_i2c_config mss_i2c_config_##n = { \
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.i2c_base_addr = DT_INST_REG_ADDR(n), \
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.i2c_irq_base = DT_INST_IRQN(n), \
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.clock_freq = DT_INST_PROP(n, clock_frequency), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, mss_i2c_init_##n, NULL, &mss_i2c_data_##n, &mss_i2c_config_##n, \
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PRE_KERNEL_1, CONFIG_I2C_INIT_PRIORITY, &mss_i2c_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(MSS_I2C_INIT)
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