4e7950e4bd
Only reset cause is supported as there is no common unique id present on those chips. Unique ID can be put in OTP but there is no single specification for this. Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
64 lines
1.2 KiB
C
64 lines
1.2 KiB
C
/*
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* Copyright (c) 2023 Jerzy Kasenberg.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <soc.h>
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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int ret = 0;
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uint32_t reason = CRG_TOP->RESET_STAT_REG;
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uint32_t flags = 0;
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/*
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* When POR is detected other bits are not valid.
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*/
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if (reason & CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk) {
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flags = RESET_POR;
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} else {
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if (reason & CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk) {
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flags |= RESET_PIN;
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}
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if (reason & CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk) {
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flags |= RESET_SOFTWARE;
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}
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if (reason & CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk) {
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flags |= RESET_WATCHDOG;
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}
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if (reason & CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk) {
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flags |= RESET_WATCHDOG;
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}
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if (reason & CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk) {
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flags |= RESET_DEBUG;
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}
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}
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*cause = flags;
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return ret;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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int ret = 0;
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CRG_TOP->RESET_STAT_REG = 0;
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return ret;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = (RESET_PIN
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| RESET_SOFTWARE
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| RESET_POR
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| RESET_WATCHDOG
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| RESET_DEBUG);
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return 0;
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}
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