e1e78a5f08
This commit adds support for the hwinfo for Apollo4P SoCs Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
138 lines
3 KiB
C
138 lines
3 KiB
C
/*
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* Copyright (c) 2024 Ambiq
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <am_mcu_apollo.h>
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#include <zephyr/drivers/hwinfo.h>
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#include <string.h>
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#include <zephyr/sys/byteorder.h>
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ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
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{
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struct ambiq_hwinfo {
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/* Ambiq Chip ID0 */
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uint32_t chip_id_0;
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/* Ambiq Chip ID1 */
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uint32_t chip_id_1;
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/* Ambiq Factory Trim Revision */
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/* Can be used in Ambiq HAL for additional code support */
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uint32_t factory_trim_version;
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};
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struct ambiq_hwinfo dev_hw_info = {0};
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/* Contains the HAL hardware information about the device. */
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am_hal_mcuctrl_device_t mcu_ctrl_device;
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am_hal_mram_info_read(1, AM_REG_INFO1_TRIM_REV_O / 4, 1, &dev_hw_info.factory_trim_version);
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am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &mcu_ctrl_device);
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dev_hw_info.chip_id_0 = mcu_ctrl_device.ui32ChipID0;
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dev_hw_info.chip_id_1 = mcu_ctrl_device.ui32ChipID1;
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if (length > sizeof(dev_hw_info)) {
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length = sizeof(dev_hw_info);
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}
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dev_hw_info.chip_id_0 = BSWAP_32(dev_hw_info.chip_id_0);
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dev_hw_info.chip_id_1 = BSWAP_32(dev_hw_info.chip_id_1);
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dev_hw_info.factory_trim_version = BSWAP_32(dev_hw_info.factory_trim_version);
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memcpy(buffer, &dev_hw_info, length);
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return length;
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}
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int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
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{
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uint32_t flags = 0;
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uint32_t reset_status = 0;
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am_hal_reset_status_t status = {0};
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/* Print out reset status register upon entry */
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am_hal_reset_status_get(&status);
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reset_status = status.eStatus;
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/* EXTERNAL PIN */
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if (reset_status & AM_HAL_RESET_STATUS_EXTERNAL) {
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flags |= RESET_PIN;
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}
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/* POWER CYCLE */
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if (reset_status & AM_HAL_RESET_STATUS_POR) {
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flags |= RESET_POR;
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}
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/* BROWNOUT DETECTOR */
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if (reset_status & AM_HAL_RESET_STATUS_BOD) {
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flags |= RESET_BROWNOUT;
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}
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/* SOFTWARE POR */
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if (reset_status & AM_HAL_RESET_STATUS_SWPOR) {
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flags |= RESET_SOFTWARE;
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}
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/* SOFTWARE POI */
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if (reset_status & AM_HAL_RESET_STATUS_SWPOI) {
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flags |= RESET_SOFTWARE;
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}
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/* DEBUGGER */
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if (reset_status & AM_HAL_RESET_STATUS_DEBUGGER) {
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flags |= RESET_DEBUG;
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}
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/* WATCHDOG */
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if (reset_status & AM_HAL_RESET_STATUS_WDT) {
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flags |= RESET_WATCHDOG;
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}
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/* BOUNREG */
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if (reset_status & AM_HAL_RESET_STATUS_BOUNREG) {
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flags |= RESET_HARDWARE;
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}
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/* BOCORE */
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if (reset_status & AM_HAL_RESET_STATUS_BOCORE) {
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flags |= RESET_HARDWARE;
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}
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/* BOMEM */
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if (reset_status & AM_HAL_RESET_STATUS_BOMEM) {
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flags |= RESET_HARDWARE;
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}
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/* BOHPMEM */
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if (reset_status & AM_HAL_RESET_STATUS_BOHPMEM) {
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flags |= RESET_HARDWARE;
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}
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*cause = flags;
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return 0;
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}
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int z_impl_hwinfo_clear_reset_cause(void)
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{
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/* SBL maintains the RSTGEN->STAT register in
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* INFO1 space even upon clearing RSTGEN->STAT
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* register.
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* - INFO1_RESETSTATUS
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*/
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return -ENOSYS;
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}
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int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
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{
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*supported = RESET_PIN
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| RESET_SOFTWARE
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| RESET_POR
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| RESET_WATCHDOG
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| RESET_HARDWARE
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| RESET_BROWNOUT;
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return 0;
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}
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