130 lines
4.3 KiB
C
130 lines
4.3 KiB
C
/*
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* Copyright (c) 2021, Yonatan Schachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#include <ch32v00x.h>
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#define DT_DRV_COMPAT wch_gpio
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struct gpio_ch32v00x_config {
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struct gpio_driver_config common;
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GPIO_TypeDef *regs;
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const struct device *clock_dev;
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uint8_t clock_id;
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};
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struct gpio_ch32v00x_data {
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struct gpio_driver_data common;
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};
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static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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GPIO_TypeDef *regs = config->regs;
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if (regs == GPIOD && (pin == 7 || pin == 1)) {
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/* D7 is NRST and D1 is SWIO. Prevent configuring them to prevent bricking
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* the chip.
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*/
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return -EACCES;
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}
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uint32_t cfg = regs->CFGLR & ~(0x0F << (4 * pin));
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if ((flags & GPIO_OUTPUT) != 0) {
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cfg |= (0x01 << (4 * pin));
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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regs->BSHR = 1 << pin;
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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regs->BSHR = 1 << (16 + pin);
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}
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} else if ((flags & GPIO_INPUT) != 0) {
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cfg |= (0x10 << (4 * pin));
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} else {
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cfg |= (0x00 << (4 * pin));
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}
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regs->CFGLR = cfg;
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return 0;
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}
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static int gpio_ch32v00x_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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*value = config->regs->INDR;
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return 0;
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}
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static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask,
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uint32_t value)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BSHR = ((~value & mask) << 16) | (value & mask);
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return 0;
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}
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static int gpio_ch32v00x_port_set_bits_raw(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BSHR = pins;
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return 0;
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}
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static int gpio_ch32v00x_port_clear_bits_raw(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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config->regs->BCR = pins;
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return 0;
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}
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static int gpio_ch32v00x_port_toggle_bits(const struct device *dev, uint32_t pins)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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uint32_t changed = (config->regs->OUTDR ^ pins) & pins;
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config->regs->BSHR = (changed & pins) | (~changed & pins) << 16;
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return 0;
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}
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static const struct gpio_driver_api gpio_ch32v00x_driver_api = {
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.pin_configure = gpio_ch32v00x_configure,
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.port_get_raw = gpio_ch32v00x_port_get_raw,
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.port_set_masked_raw = gpio_ch32v00x_port_set_masked_raw,
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.port_set_bits_raw = gpio_ch32v00x_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ch32v00x_port_clear_bits_raw,
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.port_toggle_bits = gpio_ch32v00x_port_toggle_bits,
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};
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static int gpio_ch32v00x_init(const struct device *dev)
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{
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const struct gpio_ch32v00x_config *config = dev->config;
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clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id);
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return 0;
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}
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#define GPIO_CH32V00X_INIT(idx) \
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static const struct gpio_ch32v00x_config gpio_ch32v00x_##idx##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
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}, \
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.regs = (GPIO_TypeDef *)DT_INST_REG_ADDR(idx), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_id = DT_INST_CLOCKS_CELL(idx, id), \
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}; \
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\
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static struct gpio_ch32v00x_data gpio_ch32v00x_##idx##_data; \
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\
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DEVICE_DT_INST_DEFINE(idx, gpio_ch32v00x_init, NULL, &gpio_ch32v00x_##idx##_data, \
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&gpio_ch32v00x_##idx##_config, POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_ch32v00x_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_CH32V00X_INIT)
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