273 lines
6.4 KiB
C
273 lines
6.4 KiB
C
/*
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* Copyright (c) 2024 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CACHE_CACHE_ANDES_L2_H_
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#define ZEPHYR_DRIVERS_CACHE_CACHE_ANDES_L2_H_
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/syscon.h>
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#define L2C_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, andestech_l2c), 0)
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/* L2 cache Register Offset */
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#define L2C_CONFIG (L2C_BASE + 0x00)
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#define L2C_CTRL (L2C_BASE + 0x08)
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#define L2C_CCTLCMD(hart_id) \
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(L2C_BASE + 0x40 + (hart_id * l2_cache_cfg.cmd_offset))
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#define L2C_CCTLACC(hart_id) \
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(L2C_BASE + 0x48 + (hart_id * l2_cache_cfg.cmd_offset))
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#define L2C_CCTLST(hart_id) \
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(L2C_BASE + 0x80 + (hart_id * l2_cache_cfg.status_offset))
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/* L2 cache config registers bitfields */
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#define L2C_CONFIG_SIZE_SHIFT 7
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#define L2C_CONFIG_MAP BIT(20)
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#define L2C_CONFIG_VERSION_SHIFT 24
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/* L2 cache control registers bitfields */
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#define L2C_CTRL_CEN BIT(0)
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#define L2C_CTRL_IPFDPT_3 GENMASK(4, 3)
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#define L2C_CTRL_DPFDPT_8 GENMASK(7, 6)
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/* L2 cache CCTL Access Line registers bitfields */
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#define L2C_CCTLACC_WAY_SHIFT 28
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/* L2 CCTL Command */
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#define CCTL_L2_IX_INVAL 0x00
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#define CCTL_L2_IX_WB 0x01
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#define CCTL_L2_PA_INVAL 0x08
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#define CCTL_L2_PA_WB 0x09
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#define CCTL_L2_PA_WBINVAL 0x0a
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#define CCTL_L2_WBINVAL_ALL 0x12
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#define K_CACHE_WB BIT(0)
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#define K_CACHE_INVD BIT(1)
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#define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
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struct nds_l2_cache_config {
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uint32_t size;
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uint32_t cmd_offset;
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uint32_t status_offset;
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uint16_t status_shift;
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uint8_t version;
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};
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static struct nds_l2_cache_config l2_cache_cfg;
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static ALWAYS_INLINE int nds_l2_cache_is_inclusive(void)
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{
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return IS_ENABLED(CONFIG_L2C_INCLUSIVE_POLICY) &&
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(l2_cache_cfg.version > 15);
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}
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static ALWAYS_INLINE void nds_l2_cache_wait_status(uint8_t hart_id)
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{
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uint32_t status;
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do {
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status = sys_read32(L2C_CCTLST(hart_id));
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status >>= hart_id * l2_cache_cfg.status_shift;
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status &= BIT_MASK(4);
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} while (status == 1);
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}
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static ALWAYS_INLINE int nds_l2_cache_all(int op)
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{
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/* L2 cache fixed to 64 byte cache line size and 16 way */
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const unsigned long line_size = 64, ways = 16;
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unsigned long sets, index, cmd;
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uint8_t hart_id;
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unsigned long status = csr_read(mstatus);
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if (!l2_cache_cfg.size) {
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return -ENOTSUP;
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}
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if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
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if ((status & MSTATUS_MPRV) && !(status & MSTATUS_MPP)) {
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if (!nds_l2_cache_is_inclusive()) {
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return -ENOTSUP;
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}
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}
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}
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switch (op) {
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case K_CACHE_WB:
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cmd = CCTL_L2_IX_WB;
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break;
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case K_CACHE_INVD:
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cmd = CCTL_L2_IX_INVAL;
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break;
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case K_CACHE_WB_INVD:
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cmd = CCTL_L2_WBINVAL_ALL;
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break;
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default:
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return -ENOTSUP;
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}
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hart_id = arch_proc_id();
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if (op == K_CACHE_WB_INVD) {
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sys_write32(CCTL_L2_WBINVAL_ALL, L2C_CCTLCMD(hart_id));
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/* Wait L2 CCTL Commands finished */
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nds_l2_cache_wait_status(hart_id);
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} else {
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sets = l2_cache_cfg.size / (ways * line_size);
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/* Invalidate all cache line by each way and each set */
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for (int j = 0; j < ways; j++) {
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/* Index of way */
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index = j << L2C_CCTLACC_WAY_SHIFT;
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for (int i = 0; i < sets; i++) {
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/* Index of set */
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index += line_size;
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/* Invalidate each cache line */
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sys_write32(index, L2C_CCTLACC(hart_id));
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sys_write32(cmd, L2C_CCTLCMD(hart_id));
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/* Wait L2 CCTL Commands finished */
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nds_l2_cache_wait_status(hart_id);
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}
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}
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}
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return 0;
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}
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static ALWAYS_INLINE int nds_l2_cache_range(void *addr, size_t size, int op)
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{
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const unsigned long line_size = 64;
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unsigned long last_byte, align_addr, cmd;
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uint8_t hart_id;
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if (!l2_cache_cfg.size) {
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return -ENOTSUP;
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}
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switch (op) {
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case K_CACHE_WB:
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cmd = CCTL_L2_PA_WB;
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break;
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case K_CACHE_INVD:
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cmd = CCTL_L2_PA_INVAL;
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break;
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case K_CACHE_WB_INVD:
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cmd = CCTL_L2_PA_WBINVAL;
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break;
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default:
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return -ENOTSUP;
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}
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last_byte = (unsigned long)addr + size - 1;
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align_addr = ROUND_DOWN(addr, line_size);
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hart_id = arch_proc_id();
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while (align_addr <= last_byte) {
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sys_write32(align_addr, L2C_CCTLACC(hart_id));
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sys_write32(cmd, L2C_CCTLCMD(hart_id));
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align_addr += line_size;
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/* Wait L2 CCTL Commands finished */
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nds_l2_cache_wait_status(hart_id);
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}
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return 0;
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}
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static ALWAYS_INLINE void nds_l2_cache_enable(void)
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{
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if (l2_cache_cfg.size) {
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uint32_t l2c_ctrl = sys_read32(L2C_CTRL);
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if (!(l2c_ctrl & L2C_CTRL_CEN)) {
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WRITE_BIT(l2c_ctrl, 0, true);
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sys_write32(l2c_ctrl, L2C_CTRL);
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}
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}
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}
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static ALWAYS_INLINE void nds_l2_cache_disable(void)
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{
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if (l2_cache_cfg.size) {
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uint32_t l2c_ctrl = sys_read32(L2C_CTRL);
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if (l2c_ctrl & L2C_CTRL_CEN) {
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WRITE_BIT(l2c_ctrl, 0, false);
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sys_write32(l2c_ctrl, L2C_CTRL);
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}
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}
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}
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static ALWAYS_INLINE int nds_l2_cache_init(void)
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{
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unsigned long line_size;
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#if IS_ENABLED(CONFIG_SYSCON)
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(syscon), andestech_atcsmu100, okay)
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uint32_t system_cfg;
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const struct device *syscon_dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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if (device_is_ready(syscon_dev)) {
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/* Check L2 cache feature from SMU */
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syscon_read_reg(syscon_dev, 0x08, &system_cfg);
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/* Platform doesn't support L2 cache controller */
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if (!(system_cfg & BIT(8))) {
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l2_cache_cfg.size = 0;
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return 0;
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}
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} else {
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LOG_ERR("Andes cache driver should be initialized after "
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"syscon driver initialization");
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return 0;
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}
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#endif /* andestech_atcsmu100 dts node status okay */
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#endif /* IS_ENABLED(CONFIG_SYSCON) */
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uint32_t l2c_ctrl;
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line_size = (sys_read32(L2C_CONFIG) >> L2C_CONFIG_SIZE_SHIFT) & BIT_MASK(7);
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l2_cache_cfg.size = line_size * 128 * 1024;
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if (sys_read32(L2C_CONFIG) & L2C_CONFIG_MAP) {
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l2_cache_cfg.cmd_offset = 0x10;
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l2_cache_cfg.status_offset = 0;
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l2_cache_cfg.status_shift = 4;
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} else {
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l2_cache_cfg.cmd_offset = 0x1000;
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l2_cache_cfg.status_offset = 0x1000;
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l2_cache_cfg.status_shift = 0;
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}
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l2_cache_cfg.version = (sys_read32(L2C_CONFIG) >> L2C_CONFIG_VERSION_SHIFT) & BIT_MASK(8);
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/* Initializing L2 cache instruction, data prefetch depth */
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l2c_ctrl = sys_read32(L2C_CTRL);
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l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
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/* Writeback and invalidate all I/D-Cache before setting L2C */
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__asm__ volatile ("fence.i");
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sys_write32(l2c_ctrl, L2C_CTRL);
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if (IS_ENABLED(CONFIG_SMP)) {
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if (l2_cache_cfg.size) {
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l2c_ctrl = sys_read32(L2C_CTRL);
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if (!(l2c_ctrl & L2C_CTRL_CEN)) {
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WRITE_BIT(l2c_ctrl, 0, true);
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sys_write32(l2c_ctrl, L2C_CTRL);
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}
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}
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}
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return l2_cache_cfg.size;
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}
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#endif /* ZEPHYR_DRIVERS_CACHE_CACHE_ANDES_L2_H_ */
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