e34f1cee06
Implement a set of per-cpu trampoline stacks which all interrupts and exceptions will initially land on, and also as an intermediate stack for privilege changes as we need some stack space to swap page tables. Set up the special trampoline page which contains all the trampoline stacks, TSS, and GDT. This page needs to be present in the user page tables or interrupts don't work. CPU exceptions, with KPTI turned on, are treated as interrupts and not traps so that we have IRQs locked on exception entry. Add some additional macros for defining IDT entries. Add special handling of locore text/rodata sections when creating user mode page tables on x86-64. Restore qemu_x86_64 to use KPTI, and remove restrictions on enabling user mode on x86-64. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
14 lines
270 B
Text
14 lines
270 B
Text
# SPDX-License-Identifier: Apache-2.0
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config BOARD_QEMU_X86
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bool "QEMU x86"
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depends on SOC_IA32
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select QEMU_TARGET
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select CPU_HAS_FPU
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select HAS_COVERAGE_SUPPORT
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config BOARD_QEMU_X86_64
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bool "QEMU x86_64"
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depends on SOC_IA32
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select QEMU_TARGET
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select X86_64
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