2a82acc6d6
Remove CONFIG_CLOCK_STM32_PLL_XTPRE as it is not longer being defined or used. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
32 lines
712 B
Plaintext
32 lines
712 B
Plaintext
# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_STM32F103XE=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# enable uart driver
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CONFIG_SERIAL=y
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# enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# enable pinmux
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CONFIG_PINMUX=y
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# enable GPIO
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CONFIG_GPIO=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# APB1 clock must not to exceed 36MHz limit
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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