/*
 * Copyright 2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/clock/scg_k4.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/i2c/i2c.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m33f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
			};
		};
	};

	soc {
		ctcm: sram@14000000 {
			ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
			#address-cells = <1>;
			#size-cells = <1>;

			ctcm0: code_memory@0 {
				compatible = "mmio-sram";
				reg = <0x0 DT_SIZE_K(16)>;
			};
		};

		stcm: sram@30000000 {
			ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
			#address-cells = <1>;
			#size-cells = <1>;

			stcm0: system_memory@0 {
				compatible = "mmio-sram";
				reg = <0x0 DT_SIZE_K(64)>;
			};

			stcm1: system_memory@1a000 {
				compatible = "zephyr,memory-region","mmio-sram";
				reg = <0x1a000 DT_SIZE_K(8)>;
				zephyr,memory-region = "RetainedMem";
			};
		};

		smu2: sram@489c0000 {
			ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		peripheral: peripheral@50000000 {
			ranges = <0x0 0x50000000 0x10000000>;

			fmu: memory-controller@20000 {
				ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
				#address-cells = <1>;
				#size-cells = <1>;

				compatible = "nxp,iap-msf1";
				reg = <0x20000 0x1000>;
				interrupts = <27 0>;
				status = "disabled";

				flash: flash@0 {
					reg = <0x0 DT_SIZE_M(1)>;
					compatible = "soc-nv-flash";
					write-block-size = <16>;
					erase-block-size = <8192>;
				};
			};
		};
	};

	pinctrl: pinctrl {
		compatible = "nxp,kinetis-pinctrl";
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};

&peripheral {
	#address-cells = <1>;
	#size-cells = <1>;

	scg: scg@1e000 {
		compatible = "nxp,scg-k4";
		reg = <0x1e000 0x404>;
		#clock-cells = <2>;
	};

	porta: pinmux@42000 {
		compatible = "nxp,kinetis-pinmux";
		reg = <0x42000 0xe0>;
		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
	};

	portb: pinmux@43000 {
		compatible = "nxp,kinetis-pinmux";
		reg = <0x43000 0xe0>;
		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
	};

	portc: pinmux@44000 {
		compatible = "nxp,kinetis-pinmux";
		reg = <0x44000 0xe0>;
		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
	};

	portd: pinmux@45000 {
		compatible = "nxp,kinetis-pinmux";
		reg = <0x45000 0xe0>;
		clocks = <&scg SCG_K4_SLOW_CLK 0>;
	};

	lpuart0: lpuart@38000 {
		compatible = "nxp,kinetis-lpuart";
		reg = <0x38000 0x34>;
		interrupts = <44 0>;
		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
		status = "disabled";
	};

	lpuart1: lpuart@39000 {
		compatible = "nxp,kinetis-lpuart";
		reg = <0x39000 0x34>;
		interrupts = <45 0>;
		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
		status = "disabled";
	};

	gpioa: gpio@10000{
		compatible = "nxp,kinetis-gpio";
		status = "disabled";
		gpio-controller;
		#gpio-cells = <2>;
		nxp,kinetis-port = <&porta>;
		reg = <0x10000 0x128>;
		interrupts = <59 0>, <60 0>;
	};

	gpiob: gpio@20000{
		compatible = "nxp,kinetis-gpio";
		status = "disabled";
		gpio-controller;
		#gpio-cells = <2>;
		nxp,kinetis-port = <&portb>;
		reg = <0x20000 0x128>;
		interrupts = <61 0>, <62 0>;
	};

	gpioc: gpio@30000{
		compatible = "nxp,kinetis-gpio";
		status = "disabled";
		gpio-controller;
		#gpio-cells = <2>;
		nxp,kinetis-port = <&portc>;
		reg = <0x30000 0x128>;
		interrupts = <63 0>, <64 0>;
	};

	gpiod: gpio@46000{
		compatible = "nxp,kinetis-gpio";
		status = "disabled";
		gpio-controller;
		#gpio-cells = <2>;
		nxp,kinetis-port = <&portd>;
		reg = <0x46000 0x128>;
		interrupts = <65 0>, <66 0>;
	};

	vbat: vbat@2b000 {
		reg = <0x2b000 0x400>;
		interrupts = <74 0>;
	};
};