/*
 * Copyright (c) 2019 Linaro Limited
 * Copyright (c) 2019 Centaur Analytics, Inc
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m7";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv7m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <8>;
			};
		};
	};

	soc {
		flash-controller@52002000 {
			compatible = "st,stm32h7-flash-controller";
			label = "FLASH_CTRL";
			reg = <0x52002000 0x400>;
			interrupts = <4 0>;

			#address-cells = <1>;
			#size-cells = <1>;
		};

		rcc: rcc@58024400 {
			compatible = "st,stm32-rcc";
			#clock-cells = <2>;
			reg = <0x58024400 0x400>;
			label = "STM32_CLK_RCC";
		};

		pinctrl: pin-controller@58020000 {
			compatible = "st,stm32-pinmux";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x58020000 0x2400>;

			gpioa: gpio@58020000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58020000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
				label = "GPIOA";
			};

			gpiob: gpio@58020400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58020400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
				label = "GPIOB";
			};

			gpioc: gpio@58020800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58020800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
				label = "GPIOC";
			};

			gpiod: gpio@58020C00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58020C00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
				label = "GPIOD";
			};

			gpioe: gpio@58021000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58021000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
				label = "GPIOE";
			};

			gpiof: gpio@58021400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58021400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
				label = "GPIOF";
			};

			gpiog: gpio@58021800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58021800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
				label = "GPIOG";
			};

			gpioh: gpio@58021C00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58021C00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
				label = "GPIOH";
			};

			gpioi: gpio@58022000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58022000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
				label = "GPIOI";
			};

			gpioj: gpio@58022400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58022400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
				label = "GPIOJ";
			};

			gpiok: gpio@58022800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x58022800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
				label = "GPIOK";
			};
		};

		wwdg1: watchdog@50003000 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x50003000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
			interrupts = <0 7>;
			status = "disabled";
			label = "WWDG_1";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
			interrupts = <37 0>;
			status = "disabled";
			label = "UART_1";
		};
		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			interrupts = <38 0>;
			status = "disabled";
			label = "UART_2";
		};
		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			interrupts = <39 0>;
			status = "disabled";
			label = "UART_3";
		};
		uart4: serial@40004c00 {
			compatible ="st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			interrupts = <52 0>;
			status = "disabled";
			label = "UART_4";
		};
		uart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
			interrupts = <53 0>;
			status = "disabled";
			label = "UART_5";
		};
		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
			interrupts = <71 0>;
			status = "disabled";
			label = "UART_6";
		};
		uart7: serial@40007800 {
			compatible = "st,stm32-uart";
			reg = <0x40007800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
			interrupts = <82 0>;
			status = "disabled";
			label = "UART_7";
		};
		uart8: serial@40007c00 {
			compatible = "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
			interrupts = <83 0>;
			status = "disabled";
			label = "UART_8";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};