/* * Copyright (c) 2019 Richard Osterloh * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4f"; reg = <0>; }; }; sram0: memory@20000000 { compatible = "mmio-sram"; }; soc { rcc: rcc@40021000 { compatible = "st,stm32-rcc"; #clock-cells = <2>; reg = <0x40021000 0x400>; label = "STM32_CLK_RCC"; }; pinctrl: pin-controller@48000000 { compatible = "st,stm32-pinmux"; #address-cells = <1>; #size-cells = <1>; reg = <0x48000000 0x2000>; gpioa: gpio@48000000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; label = "GPIOA"; }; gpiob: gpio@48000400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; label = "GPIOB"; }; gpioc: gpio@48000800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; label = "GPIOC"; }; gpiod: gpio@48000c00 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; label = "GPIOD"; }; gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; label = "GPIOE"; }; gpiof: gpio@48001400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; label = "GPIOF"; }; gpiog: gpio@48001800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; label = "GPIOG"; }; }; }; }; &nvic { arm,num-irq-priority-bits = <4>; };