/*
 * Copyright (c) 2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <mem.h>
#include <xtensa/xtensa.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/clock/esp32_clock.h>
#include <dt-bindings/interrupt-controller/esp-xtensa-intmux.h>

/ {
	chosen {
		zephyr,entropy = &trng0;
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx6";
			reg = <0>;
			clock-source = <ESP32_CLK_SRC_PLL>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx6";
			reg = <1>;
			clock-source = <ESP32_CLK_SRC_PLL>;
		};

	};

	wifi: wifi {
		compatible = "espressif,esp32-wifi";
		status = "disabled";
	};

	soc {
		sram0: memory@3ffb0000 {
			compatible = "mmio-sram";
			reg = <0x3FFB0000 0x50000>;
		};

		intc: interrupt-controller@3ff00104 {
			#interrupt-cells = <1>;
			compatible = "espressif,esp32-intc";
			interrupt-controller;
			reg = <0x3ff00104 0x114>;
			label = "INTC_0";
			status = "okay";
		};

		rtc: rtc@3ff48000 {
			compatible = "espressif,esp32-rtc";
			reg = <0x3ff48000 0x0D8>;
			label = "RTC";
			xtal-freq = <ESP32_CLK_XTAL_40M>;
			xtal-div = <0>;
			#clock-cells = <1>;
			status = "ok";
		};

		flash: flash-controller@3ff42000 {
			compatible = "espressif,esp32-flash-controller";
			label = "FLASH_CTRL";
			reg = <0x3ff42000 0x1000>;
			/* interrupts = <3 0>; */

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@0 {
				compatible = "soc-nv-flash";
				label = "FLASH_ESP32";
				reg = <0 0x400000>;
				erase-block-size = <4096>;
				write-block-size = <4>;
			};
		};

		uart0: uart@3ff40000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff40000 0x400>;
			interrupts = <UART0_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "UART_0";
			clocks = <&rtc ESP32_UART0_MODULE>;
			status = "disabled";
		};

		uart1: uart@3ff50000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff50000 0x400>;
			interrupts = <UART1_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "UART_1";
			clocks = <&rtc ESP32_UART1_MODULE>;
			status = "disabled";
		};

		uart2: uart@3ff6e000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff6E000 0x400>;
			interrupts = <UART2_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "UART_2";
			clocks = <&rtc ESP32_UART2_MODULE>;
			status = "disabled";
		};

		pinmux: pinmux@3ff49000 {
			compatible = "espressif,esp32-pinmux";
			reg = <0x3ff49000 0x94>;
		};

		gpio0: gpio@3ff44000 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3ff44000 0x800>;
			interrupts = <GPIO_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "GPIO_0";
			ngpios = <32>;   /* 0..31 */
		};

		gpio1: gpio@3ff44800 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3ff44800 0x800>;
			interrupts = <GPIO_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "GPIO_1";
			ngpios = <8>;   /* 32..39 */
		};

		i2c0: i2c@3ff53000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3ff53000 0x1000>;
			interrupts = <I2C_EXT0_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "I2C_0";
			clocks = <&rtc ESP32_I2C_EXT0_MODULE>;
			status = "disabled";
		};

		i2c1: i2c@3ff67000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3ff67000 0x1000>;
			interrupts = <I2C_EXT1_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "I2C_1";
			clocks = <&rtc ESP32_I2C_EXT1_MODULE>;
			status = "disabled";
		};

		trng0: trng@3ff75144 {
			compatible = "espressif,esp32-trng";
			reg = <0x3FF75144 0x4>;
			/* interrupts = <33 0>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
			label = "TRNG_0";
			status = "disabled";
		};

		wdt0: watchdog@3ff5f048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3ff5f048 0x20>;
			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "WDT_0";
			status = "okay";
		};

		wdt1: watchdog@3ff60048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3ff60048 0x20>;
			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "WDT_1";
			status = "disabled";
		};

		spi2: spi@3ff64000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3ff64000 DT_SIZE_K(4)>;
			interrupts = <SPI2_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "SPI_2";
			clocks = <&rtc ESP32_SPI2_MODULE>;
			status = "disabled";
		};

		spi3: spi@3ff65000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3ff65000 DT_SIZE_K(4)>;
			interrupts = <SPI3_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "SPI_3";
			clocks = <&rtc ESP32_SPI3_MODULE>;
			status = "disabled";
		};

		timer0: counter@3ff5f000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff5f000 DT_SIZE_K(4)>;
			interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "TIMG0_T0";
			status = "disabled";
		};

		timer1: counter@3ff5f024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff5f024 DT_SIZE_K(4)>;
			interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "TIMG0_T1";
			status = "disabled";
		};

		timer2: counter@3ff60000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff60000 DT_SIZE_K(4)>;
			interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "TIMG1_T0";
			status = "disabled";
		};

		timer3: counter@3ff60024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3ff60024 DT_SIZE_K(4)>;
			interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			label = "TIMG1_T1";
			status = "disabled";
		};
	};

};