/*
 * Copyright (c) 2025 Analog Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>

&sram0 {
	reg = <0x20000000 DT_SIZE_M(1)>;
};

&flash0 {
	reg = <0x10000000 DT_SIZE_M(3)>;
	erase-block-size = <16384>;
};

&clk_ipo {
	clock-frequency = <DT_FREQ_M(120)>;
};

&clk_iso {
	clock-frequency = <DT_FREQ_M(50)>;
};

/delete-node/ &clk_erfo;

/delete-node/ &i2c2;

/delete-node/ &trng;

&pinctrl {
	reg = <0x40008000 0x4000>;

	gpio2: gpio@4000a000 {
		reg = <0x4000a000 0x1000>;
		compatible = "adi,max32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupts = <26 0>;
		clocks = <&gcr ADI_MAX32_CLOCK_BUS0 2>;
		status = "disabled";
	};

	gpio3: gpio@4000b000 {
		reg = <0x4000b000 0x1000>;
		compatible = "adi,max32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupts = <58 0>;
		clocks = <&gcr ADI_MAX32_CLOCK_BUS1 6>;
		status = "disabled";
	};
};

/* MAX32650 extra peripherals. */
/ {
	soc {
		trng: trng@400b5000 {
			compatible = "adi,max32-trng";
			reg = <0x400b5000 0x1000>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>;
			status = "disabled";
		};

		timer4: timer@40014000 {
			compatible = "adi,max32-timer";
			reg = <0x40014000 0x1000>;
			interrupts = <9 0>;
			status = "disabled";
			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 19>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
			prescaler = <1>;

			counter {
				compatible = "adi,max32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "adi,max32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer5: timer@40015000 {
			compatible = "adi,max32-timer";
			reg = <0x40015000 0x1000>;
			interrupts = <10 0>;
			status = "disabled";
			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 20>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
			prescaler = <1>;

			counter {
				compatible = "adi,max32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "adi,max32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};
	};
};