# STM32H7 PLL configuration options # Copyright (c) 2019 Linaro # SPDX-License-Identifier: Apache-2.0 if SOC_SERIES_STM32H7X # Bus clocks configuration options config CLOCK_STM32_D1CPRE int "D1 Domain, CPU1 clock prescaler" default 1 range 1 512 help D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. config CLOCK_STM32_HPRE int "hclk prescaler, D2 domain (CPU2) Clock prescaler" default 1 range 1 512 help hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. config CLOCK_STM32_D2PPRE1 int "APB1 prescaler" default 1 range 1 16 help APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16 config CLOCK_STM32_D2PPRE2 int "D2 DOMAIN, APB2 prescaler" default 1 range 1 16 help APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16 config CLOCK_STM32_D1PPRE int "D1 DOMAIN, APB3 prescaler" default 1 range 1 16 help APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16 config CLOCK_STM32_D3PPRE int "APB4 prescaler" default 1 range 1 16 help APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16 # PLL settings config CLOCK_STM32_PLL_M_DIVISOR int "PLL divisor" depends on CLOCK_STM32_SYSCLK_SRC_PLL default 32 range 0 63 help PLL divisor, allowed values: 0-63. config CLOCK_STM32_PLL_N_MULTIPLIER int "PLL1 VCO multiplier" depends on CLOCK_STM32_SYSCLK_SRC_PLL default 129 range 4 512 help PLL multiplier, allowed values: 4-512. config CLOCK_STM32_PLL_P_DIVISOR int "PLL P Divisor" depends on CLOCK_STM32_SYSCLK_SRC_PLL default 2 range 1 128 help PLL P Output divisor, allowed values: 1-128. config CLOCK_STM32_PLL_Q_DIVISOR int "PLL Q Divisor" depends on CLOCK_STM32_SYSCLK_SRC_PLL default 2 range 1 128 help PLL Q Output divisor, allowed values: 1-128. config CLOCK_STM32_PLL_R_DIVISOR int "PLL R Divisor" depends on CLOCK_STM32_SYSCLK_SRC_PLL default 2 range 1 128 help PLL R Output divisor, allowed values: 1-128. endif # SOC_SERIES_STM32H7X