.github/workflows/compliance.yml

@@ -23,21 +23,6 @@ jobs:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
 
-    - name: Rebase onto the target branch
-      env:
-        BASE_REF: ${{ github.base_ref }}
-      run: |
-        git config --global user.email "you@example.com"
-        git config --global user.name "Your Name"
-        git remote -v
-        # Ensure there's no merge commits in the PR
-        [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
-        (echo "::error ::Merge commits not allowed, rebase instead";false)
-        git rebase origin/${BASE_REF}
-        git clean -f -d
-        # debug
-        git log  --pretty=oneline | head -n 10
-
     - name: Set up Python
       uses: actions/setup-python@v5
       with:
@@ -53,11 +38,23 @@ jobs:
       run: |
         pip3 install setuptools
         pip3 install wheel
-        pip3 install -r scripts/requirements-compliance.txt
+        pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff sphinx-lint ruff
         pip3 install west
 
     - name: west setup
+      env:
+        BASE_REF: ${{ github.base_ref }}
       run: |
+        git config --global user.email "you@example.com"
+        git config --global user.name "Your Name"
+        git remote -v
+        # Ensure there's no merge commits in the PR
+        [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
+        (echo "::error ::Merge commits not allowed, rebase instead";false)
+        git rebase origin/${BASE_REF}
+        git clean -f -d
+        # debug
+        git log  --pretty=oneline | head -n 10
         west init -l . || true
         west config manifest.group-filter -- +ci,-optional
         west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log

.ruff-excludes.toml

@@ -43,9 +43,108 @@
 "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
 ]
+"./doc/_extensions/zephyr/api_overview.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/application.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./doc/_extensions/zephyr/domain/__init__.py" = [
+    "B023",     # https://docs.astral.sh/ruff/rules/function-uses-loop-variable
+    "B026",     # https://docs.astral.sh/ruff/rules/star-arg-unpacking-after-keyword-arg
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F401",     # https://docs.astral.sh/ruff/rules/unused-import
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/doxybridge.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/doxyrunner.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP024",    # https://docs.astral.sh/ruff/rules/os-error-alias
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/doxytooltip/__init__.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/external_content.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/gh_utils.py" = [
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/kconfig/__init__.py" = [
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "SIM112",   # https://docs.astral.sh/ruff/rules/uncapitalized-environment-variables
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP028",    # https://docs.astral.sh/ruff/rules/yield-in-for-loop
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_extensions/zephyr/link-roles.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "UP010",    # https://docs.astral.sh/ruff/rules/unnecessary-future-import
+]
+"./doc/_extensions/zephyr/manifest_projects_table.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM114",   # https://docs.astral.sh/ruff/rules/if-with-same-arms
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./doc/_scripts/gen_boards_catalog.py" = [
+    "E401",     # https://docs.astral.sh/ruff/rules/multiple-imports-on-one-line
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./doc/_scripts/gen_devicetree_rest.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP034",    # https://docs.astral.sh/ruff/rules/extraneous-parentheses
+]
+"./doc/_scripts/gen_helpers.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
 "./doc/_scripts/redirects.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
 ]
+"./doc/conf.py" = [
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "F821",     # https://docs.astral.sh/ruff/rules/undefined-name
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+]
+"./doc/develop/test/twister/sample_blackbox_test.py" = [
+    "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP026",    # https://docs.astral.sh/ruff/rules/deprecated-mock-import
+]
 "./modules/mbedtls/create_psa_files.py" = [
     "E101",     # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
@@ -748,6 +847,8 @@
 ]
 "./scripts/pylib/twister/expr_parser.py" = [
     "SIM103",   # https://docs.astral.sh/ruff/rules/needless-bool
+    "SIM110",   # https://docs.astral.sh/ruff/rules/reimplemented-builtin
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
     "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
 ]
 "./scripts/pylib/twister/scl.py" = [
@@ -756,9 +857,183 @@
     "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
     "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
 ]
-"./scripts/pylib/twister/twisterlib/testplan.py" = [
+"./scripts/pylib/twister/twisterlib/cmakecache.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM114",   # https://docs.astral.sh/ruff/rules/if-with-same-arms
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/config_parser.py" = [
+    "B028",     # https://docs.astral.sh/ruff/rules/no-explicit-stacklevel
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM401",   # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/coverage.py" = [
+    "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM105",   # https://docs.astral.sh/ruff/rules/suppressible-exception
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP022",    # https://docs.astral.sh/ruff/rules/replace-stdout-stderr
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/environment.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
     "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "SIM118",   # https://docs.astral.sh/ruff/rules/in-dict-keys
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP021",    # https://docs.astral.sh/ruff/rules/replace-universal-newlines
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./scripts/pylib/twister/twisterlib/handlers.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM105",   # https://docs.astral.sh/ruff/rules/suppressible-exception
+    "SIM114",   # https://docs.astral.sh/ruff/rules/if-with-same-arms
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "SIM201",   # https://docs.astral.sh/ruff/rules/negate-equal-op
+    "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP030",    # https://docs.astral.sh/ruff/rules/format-literals
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/hardwaremap.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM118",   # https://docs.astral.sh/ruff/rules/in-dict-keys
+    "UP004",    # https://docs.astral.sh/ruff/rules/useless-object-inheritance
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/harness.py" = [
+    "B009",     # https://docs.astral.sh/ruff/rules/get-attr-with-constant
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E713",     # https://docs.astral.sh/ruff/rules/not-in-test
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "F811",     # https://docs.astral.sh/ruff/rules/redefined-while-unused
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM300",   # https://docs.astral.sh/ruff/rules/yoda-conditions
+    "UP008",    # https://docs.astral.sh/ruff/rules/super-call-with-parameters
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/jobserver.py" = [
+    "SIM201",   # https://docs.astral.sh/ruff/rules/negate-equal-op
+]
+"./scripts/pylib/twister/twisterlib/mixins.py" = [
+    "UP004",    # https://docs.astral.sh/ruff/rules/useless-object-inheritance
+]
+"./scripts/pylib/twister/twisterlib/package.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+]
+"./scripts/pylib/twister/twisterlib/platform.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/quarantine.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM110",   # https://docs.astral.sh/ruff/rules/reimplemented-builtin
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/reports.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/runner.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E713",     # https://docs.astral.sh/ruff/rules/not-in-test
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM115",   # https://docs.astral.sh/ruff/rules/open-file-with-context-handler
+    "SIM201",   # https://docs.astral.sh/ruff/rules/negate-equal-op
+    "UP004",    # https://docs.astral.sh/ruff/rules/useless-object-inheritance
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./scripts/pylib/twister/twisterlib/size_calc.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/statuses.py" = [
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM401",   # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get
+]
+"./scripts/pylib/twister/twisterlib/testinstance.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+]
+"./scripts/pylib/twister/twisterlib/testplan.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "B023",     # https://docs.astral.sh/ruff/rules/function-uses-loop-variable
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "E713",     # https://docs.astral.sh/ruff/rules/not-in-test
+    "E741",     # https://docs.astral.sh/ruff/rules/ambiguous-variable-name
     "F401",     # https://docs.astral.sh/ruff/rules/unused-import
+    "F541",     # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
+    "SIM110",   # https://docs.astral.sh/ruff/rules/reimplemented-builtin
+    "SIM118",   # https://docs.astral.sh/ruff/rules/in-dict-keys
+    "SIM202",   # https://docs.astral.sh/ruff/rules/negate-not-equal-op
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+]
+"./scripts/pylib/twister/twisterlib/testsuite.py" = [
+    "B006",     # https://docs.astral.sh/ruff/rules/mutable-argument-default
+    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation
+    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
+    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
+]
+"./scripts/pylib/twister/twisterlib/twister_main.py" = [
+    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
+    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
+    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
+    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
 ]
 "./scripts/pylint/checkers/argparse-checker.py" = [
     "F821",     # https://docs.astral.sh/ruff/rules/undefined-name
@@ -786,6 +1061,7 @@
     "UP032",    # https://docs.astral.sh/ruff/rules/f-string
 ]
 "./scripts/release/list_devicetree_bindings_changes.py" = [
+    "E402",     # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "SIM117",   # https://docs.astral.sh/ruff/rules/multiple-with-statements
     "UP006",    # https://docs.astral.sh/ruff/rules/non-pep585-annotation

CMakeLists.txt

@@ -88,7 +88,6 @@ set(SYSCALL_LIST_H_TARGET      syscall_list_h_target)
 set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target)
 set(KOBJ_TYPES_H_TARGET        kobj_types_h_target)
 set(PARSE_SYSCALLS_TARGET      parse_syscalls_target)
-set(DEVICE_API_LD_TARGET       device_api_ld_target)
 
 define_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT BRIEF_DOCS " " FULL_DOCS " ")
 set_property(   GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little${ARCH}) # BFD format
@@ -883,37 +882,6 @@ add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION})
 include(${ZEPHYR_BASE}/cmake/kobj.cmake)
 gen_kobj(KOBJ_INCLUDE_PATH)
 
-# Generate sections for kernel device subsystems
-set(
-  DEVICE_API_LD_SECTIONS
-  ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.ld
-  )
-
-set(DEVICE_API_LINKER_SECTIONS_CMAKE
-    ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.cmake
-)
-
-add_custom_command(
-  OUTPUT ${DEVICE_API_LD_SECTIONS} ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-  COMMAND
-    ${PYTHON_EXECUTABLE}
-    ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py
-    --alignment ${CONFIG_LINKER_ITERABLE_SUBALIGN}
-    --input ${struct_tags_json}
-    --tag __subsystem
-    --ld-output ${DEVICE_API_LD_SECTIONS}
-    --cmake-output ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-  DEPENDS
-    ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py
-    ${struct_tags_json}
-  WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
-  )
-
-add_custom_target(${DEVICE_API_LD_TARGET}
-                  DEPENDS ${DEVICE_API_LD_SECTIONS}
-                          ${DEVICE_API_LINKER_SECTIONS_CMAKE}
-)
-
 # Add a pseudo-target that is up-to-date when all generated headers
 # are up-to-date.
 
@@ -944,7 +912,6 @@ add_dependencies(zephyr_interface
   ${SYSCALL_LIST_H_TARGET}
   ${DRIVER_VALIDATION_H_TARGET}
   ${KOBJ_TYPES_H_TARGET}
-  ${DEVICE_API_LD_TARGET}
   )
 
 add_custom_command(

MAINTAINERS.yml

@@ -4354,7 +4354,6 @@ USB:
     - samples/subsys/usb/
     - subsys/usb/
     - tests/subsys/usb/
-    - tests/drivers/build_all/usb/
     - tests/drivers/usb/
     - tests/drivers/udc/
     - doc/connectivity/usb/

arch/Kconfig

@@ -50,6 +50,7 @@ config ARM64
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select BARRIER_OPERATIONS_ARCH
 	select ARCH_HAS_DIRECTED_IPIS
 	select ARCH_HAS_DEMAND_PAGING
@@ -94,6 +95,7 @@ config X86
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	select ARCH_HAS_DEMAND_PAGING if !X86_64
 	select ARCH_HAS_DEMAND_MAPPING if ARCH_HAS_DEMAND_PAGING
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \
 					  && !BOARD_HAS_TIMING_FUNCTIONS \
 					  && !SOC_HAS_TIMING_FUNCTIONS
@@ -121,6 +123,7 @@ config RISCV
 	select ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS
 	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_THREAD_LOCAL_STORAGE
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
 	select SCHED_IPI_SUPPORTED if SMP
@@ -135,6 +138,7 @@ config XTENSA
 	select ARCH_IS_SET
 	select USE_SWITCH
 	select USE_SWITCH_SUPPORTED
+	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_TIMING_FUNCTIONS
 	select ARCH_MEM_DOMAIN_DATA if USERSPACE
@@ -577,12 +581,11 @@ config IRQ_OFFLOAD
 config IRQ_OFFLOAD_NESTED
 	bool "irq_offload() supports nested IRQs"
 	depends on IRQ_OFFLOAD
-	default y if ARM64 || X86 || RISCV || XTENSA
 	help
-	  When set by the platform layers, indicates that
+	  When set by the arch layer, indicates that irq_offload() may
-	  irq_offload() may legally be called in interrupt context to
+	  legally be called in interrupt context to cause a
-	  cause a synchronous nested interrupt on the current CPU.
+	  synchronous nested interrupt on the current CPU.  Not all
-	  Not all hardware is capable.
+	  hardware is capable.
 
 config EXCEPTION_DEBUG
 	bool "Unhandled exception debugging"

arch/arm/core/cortex_a_r/Kconfig

@@ -111,32 +111,6 @@ config CPU_CORTEX_R52
 	help
 	  This option signifies the use of a Cortex-R52 CPU
 
-config CPU_CORTEX_R52_CACHE_SEGREGATION
-	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
-	depends on CPU_CORTEX_R52
-	help
-	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
-	  Updates to the cache segregation controls are only permitted before the caches
-	  have ever been enabled, following a system reset, otherwise the update is ignored.
-
-config CPU_CORTEX_R52_ICACHE_FLASH_WAY
-	int "L1 I-Cache Flash way"
-	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
-	range 0 4
-	default 0
-	help
-	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
-	  I-Cache ways are allocated for AXIM interface.
-
-config CPU_CORTEX_R52_DCACHE_FLASH_WAY
-	int "L1 D-Cache Flash way"
-	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
-	range 0 4
-	default 0
-	help
-	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
-	  all D-Cache ways are allocated for AXIM interface.
-
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R

arch/arm/core/cortex_a_r/reset.S

@@ -56,12 +56,9 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
     cmp r0, #MODE_HYP
     bne EL1_Reset_Handler
 
-    /*
+    /* Init HSCTLR see Armv8-R AArch32 architecture profile */
-     * The HSCTLR register provides top-level control of system operation in Hyp mode.
+    ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
-     * Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32
+    mcr p15, 4, r0, c1, c0, 0
-     * architecture profile, there's no need to modify HSCTLR configuration unless
-     * Fast Interrupts need to be enabled.
-     */
 
     /* Init HACTLR: Enable EL1 access to all IMP DEF registers */
     ldr r0, =HACTLR_INIT
@@ -203,12 +200,6 @@ EL1_Reset_Handler:
 
 #endif /* CONFIG_DCLS */
 
-#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION)
-    ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY,
-                        CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY)
-    mcr p15, 1, r0, c9, c1, 0
-#endif
-
     ldr r0, =arm_cpu_boot_params
 
 #if CONFIG_MP_MAX_NUM_CPUS > 1

arch/riscv/Kconfig

@@ -16,13 +16,9 @@ config FLOAT_HARD
 	help
 	  This option enables the hard-float calling convention.
 
-choice RISCV_GP_PURPOSE
-	prompt "Purpose of the global pointer (GP) register"
-	default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
-
 config RISCV_GP
 	bool "RISC-V global pointer relative addressing"
-	depends on RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	default n
 	help
 	  Use global pointer relative addressing for small globals declared
 	  anywhere in the executable. It can benefit performance and reduce
@@ -34,6 +30,7 @@ config RISCV_GP
 
 config RISCV_CURRENT_VIA_GP
 	bool "Store current thread into the global pointer (GP) register"
+	depends on !RISCV_GP && !USERSPACE
 	depends on MP_MAX_NUM_CPUS > 1
 	select ARCH_HAS_CUSTOM_CURRENT_IMPL
 	help
@@ -41,8 +38,6 @@ config RISCV_CURRENT_VIA_GP
 	  When is enabled, calls to `arch_current_thread()` & `k_sched_current_thread_query()` will
 	  be reduced to a single register read.
 
-endchoice # RISCV_GP_PURPOSE
-
 config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
 	bool "Do not use mret outside a trap handler context"
 	depends on MULTITHREADING
@@ -153,12 +148,6 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO
 	  the RISC-V SoC needs to do something different and more than reading and
 	  writing the registers.
 
-config RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
-	bool
-	help
-	  Selected when SoC has implemented the initialization of global pointer (GP)
-	  at program start, or earlier than any instruction using GP relative addressing.
-
 config RISCV_SOC_CONTEXT_SAVE
 	bool "SOC-based context saving in IRQ handlers"
 	select RISCV_SOC_OFFSETS

arch/riscv/core/ipi_clint.c

@@ -9,11 +9,7 @@
 
 #include <zephyr/kernel.h>
 
-#define CLINT_NODE DT_NODELABEL(clint)
+#define MSIP_BASE    0x2000000UL
-#if !DT_NODE_EXISTS(CLINT_NODE)
-#error "Label 'clint' is not defined in the devicetree."
-#endif
-#define MSIP_BASE DT_REG_ADDR_RAW(CLINT_NODE)
 #define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid]
 
 static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS];

arch/riscv/core/isr.S

@@ -169,9 +169,7 @@ SECTION_FUNC(exception.entry, _isr_wrapper)
 	.option norelax
 	la gp, __global_pointer$
 	.option pop
-#elif defined(CONFIG_RISCV_CURRENT_VIA_GP)
+#endif /* CONFIG_RISCV_GP */
-	lr gp, ___cpu_t_current_OFFSET(s0)
-#endif /* CONFIG_RISCV_GP / CONFIG_RISCV_CURRENT_VIA_GP */
 
 	/* Clear our per-thread usermode flag */
 	lui t0, %tprel_hi(is_user_mode)

boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled

@@ -2,4 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_ESP32C3_042_OLED
-	select SOC_ESP32C3_FH4
+	select SOC_ESP32C3_FX4

boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi

@@ -2,7 +2,7 @@
  * Copyright (c) 2017 Piotr Mienkowski
  * Copyright (c) 2017 Justin Watson
  * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
- * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2019-2022 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,7 +17,6 @@
 		led0 = &yellow_led1;
 		pwm-led0 = &pwm_led0;
 		pwm-0 = &pwm0;
-		rtc = &rtc;
 		sw0 = &sw0_user_button;
 		sw1 = &sw1_user_button;
 		watchdog0 = &wdt;
@@ -337,10 +336,6 @@ zephyr_udc0: &usbhs {
 	};
 };
 
-&rtc {
-	status = "okay";
-};
-
 ext1_spi: &spi0 {
 };
 

boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml

@@ -22,7 +22,6 @@ supported:
   - i2s
   - pwm
   - netif:eth
-  - rtc
   - spi
   - usb_device
   - watchdog

boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml

@@ -22,7 +22,6 @@ supported:
   - i2s
   - pwm
   - netif:eth
-  - rtc
   - spi
   - usb_device
   - watchdog

boards/beagle/beaglev_fire/beaglev_fire_common.dtsi

@@ -14,28 +14,6 @@
 	compatible = "beagle,beaglev-fire", "microchip,mpfs";
 	aliases {
 	};
-
-	beaglev {
-		#address-cells = <2>;
-		#size-cells = <1>;
-
-		ddr_cached_high: memory@1000000000 {
-			compatible = "mmio-sram";
-			reg = <0x10 0x00000000 0x80000000>; /* 2GB */
-		};
-	};
-
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ddr_cached_high;
-	};
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <115200>;
-	clock-frequency = <150000000>;
 };
 
 &gpio2 {

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts

@@ -21,4 +21,16 @@
 			status = "disabled";
 		};
 	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
 };

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2048000
+ram: 3840
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts

@@ -5,9 +5,21 @@
 	model = "beagle,beaglev-fire";
 	compatible = "beagle,beaglev-fire", "microchip,mpfs";
 
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+
 	cpus {
 		cpu@0 {
 			status = "disabled";
 		};
 	};
 };
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
+};

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2048000
+ram: 3840
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts

@@ -4,4 +4,16 @@
 / {
 	model = "beagle,beaglev-fire";
 	compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram1;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <150000000>;
 };

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2048000
+ram: 3840
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/doc/index.rst

@@ -15,17 +15,11 @@ hobbyists, and researchers to explore and experiment with RISC-V technology.
 Building
 ========
 
-There are three board configurations provided for the BeagleV-Fire:
-
-* ``beaglev_fire/polarfire/e51``: Uses only the E51 core
-* ``beaglev_fire/polarfire/u54``: Uses the U54 cores
-* ``beaglev_fire/polarfire/u54/smp``: Uses the U54 cores with CONFIG_SMP=y
-
 Applications for the ``beaglev_fire`` board configuration can be built as usual:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: beaglev_fire/polarfire/u54
+   :board: beaglev_fire
    :goals: build
 
 Debugging
@@ -82,49 +76,3 @@ and load the binary:
    load
    break main
    continue
-
-Flashing
-========
-When using the PolarFire `Hart Software Services <https://github.com/polarfire-soc/hart-software-services>`_ along with Zephyr, you need to use the `hss-payload-generator <https://github.com/polarfire-soc/hart-software-services/tree/master/tools/hss-payload-generator>`_ tool to generate an image that HSS can boot.
-
-.. code-block:: yaml
-
-  set-name: 'ZephyrImage'
-
-  # Define the entry point address for each hart (U54 cores)
-  hart-entry-points:
-    u54_1: '0x1000000000'
-
-  # Define the payloads (ELF binaries or raw blobs)
-  payloads:
-    <path_to_zephyr.elf>:
-      exec-addr: '0x1000000000'  # Where Zephyr should be loaded
-      owner-hart: u54_1  # Primary hart that runs Zephyr
-      priv-mode: prv_m  # Start in Machine mode
-      skip-opensbi: true  # Boot directly without OpenSBI
-
-After generating the image, you can flash it to the board by restarting a board that's connected over USB and UART, interrupting the HSS boot process with a key press, and then running the ``mmc`` and ``usbdmsc`` commands:
-
-.. code-block:: bash
-
-  Press a key to enter CLI, ESC to skip
-  Timeout in 1 second
-  .[6.304162] Character 100 pressed
-  [6.308415] Type HELP for list of commands
-  [6.313276] >> mmc
-  [10.450867] Selecting SDCARD/MMC (fallback) as boot source ...
-  [10.457550] Attempting to select eMMC ... Passed
-  [10.712708] >> usbdmsc
-  [14.732841] initialize MMC
-  [14.736400] Attempting to select eMMC ... Passed
-  [15.168707] MMC - 512 byte pages, 512 byte blocks, 30621696 pages
-  Waiting for USB Host to connect... (CTRL-C to quit)
-  . 0 bytes written, 0 bytes read
-  USB Host connected. Waiting for disconnect... (CTRL-C to quit)
-  / 0 bytes written, 219136 bytes read
-
-This will cause the board to appear as a USB mass storage device. You can then then flash the image with ``dd`` or other tools like `BalenaEtcher <https://www.balena.io/etcher/>`_:
-
-.. code-block:: bash
-
-  dd if=<path_to_zephyr.elf> of=/dev/sdXD bs=4M status=progress oflag=sync

boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3

@@ -2,4 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_TTGO_T8C3
-	select SOC_ESP32C3_FN4
+	select SOC_ESP32C3_FX4

boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts

@@ -74,12 +74,6 @@
 			rotation = <0>;
 		};
 	};
-
-	bus_5v: bus_5v {
-		compatible = "regulator-fixed";
-		regulator-name = "bus_5v";
-		enable-gpios = <&axp192_gpio 5 GPIO_ACTIVE_HIGH>;
-	};
 };
 
 &flash0 {
@@ -188,6 +182,12 @@
 		};
 	};
 
+	bus_5v: bus_5v {
+		compatible = "regulator-fixed";
+		regulator-name = "bus_5v";
+		enable-gpios = <&axp192_gpio 5 GPIO_ACTIVE_HIGH>;
+	};
+
 	ft5336_touch: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;

boards/m5stack/stamp_c3/Kconfig.stamp_c3

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_STAMP_C3
-	select SOC_ESP32C3_FN4
+	select SOC_ESP32C3_FX4

boards/mediatek/index.rst

@@ -1,166 +0,0 @@
-.. _boards-mtk_adsp:
-
-Mediatek Audio DSPs
-###################
-
-Zephyr can be built and run on the Audio DSPs included in various
-members of the Mediatek MT8xxx series of ARM SOCs used in Chromebooks
-from various manufacturers.
-
-Two of these DSPs are in the market already, implemented via the
-MT8195 ("Kompanio 1380") and MT8186 ("Kompanio 520") SOCs.
-Development has been done on and validation performed on at least
-these devices, though more exist:
-
-  ======  =============  ===================================  =================
-  SOC     Product Name   Example Device                       ChromeOS Codename
-  ======  =============  ===================================  =================
-  MT8195  Kompanio 1380  HP Chromebook x360 13b               dojo
-  MT8186  Kompanio 520   Lenovo 300e Yoga Chromebook Gen 4    steelix
-  ======  =============  ===================================  =================
-
-Hardware
-********
-
-These devices are Xtensa DSP cores, very similar to the Intel ADSP
-series in concept (with the notable difference that these are all
-single-core devices, no parallel SMP is available, but at the same
-time there are fewer worries about the incoherent cache).
-
-Their memory space is split between dedicated, fast SRAM and ~16MB of
-much slower system DRAM.  Zephyr currently loads and links into the
-DRAM area, a convention it inherits from SOF (these devices have
-comparatively large caches which are used for all accesses, unlike
-with intel_adsp).  SRAM is used for interrupt vectors and stacks,
-currently.
-
-There is comparatively little on-device hardware.  The architecture is
-that interaction with the off-chip audio hardware (e.g. I2S codecs,
-DMIC inputs, etc...) is managed by the host kernel.  The DSP receives
-its data via a single array of custom DMA controllers.
-
-Beyond that the Zephyr-visible hardware is limited to a bounty of
-timer devices (of which Zephyr uses two), and a "mailbox"
-bidirectional interrupt source it uses to communicate with the host
-kernel.
-
-Programming and Debugging
-*************************
-
-These devices work entirely in RAM, so there is no "flash" process as
-such.  Their memory state is initialized by the host Linux
-environment.  This process works under the control of a
-``mtk_adsp_load.py`` python script, which has no dependencies outside
-the standard library and can be run (as root, of course) on any
-reasonably compatible Linux environment with a Python 3.8 or later
-interpreter.  A chromebook in development mode with the dev packages
-installed works great.  See the ChromiumOS developer library for more
-detail:
-
-* `Developer mode <https://www.chromium.org/chromium-os/developer-library/guides/device/developer-mode/>`__
-* `Dev-Install: Installing Developer and Test packages onto a Chrome OS device <https://www.chromium.org/chromium-os/developer-library/guides/device/install-software-on-base-images/>`__
-
-Once you have the device set up, the process is as simple as copying
-the ``zephyr.img`` file from the build directory to the device
-(typically via ssh) and running it with the script.  For example for
-my mt8186 device named "steelix":
-
-.. code-block:: console
-
-   user@dev_host:~$ west build -b mt8186//adsp samples/hello_world
-   ...
-   ... # build output
-   ...
-   user@dev_host:~$ scp build/zephyr/zephyr.img root@steelix:
-   user@dev_host:~$ scp soc/mediatek/mt8xxx/mtk_adsp_load.py root@steelix:
-   user@dev_host:~$ ssh steelix
-
-   root@steelix:~ # ./mtk_adsp_load.py load zephyr.img
-   *** Booting Zephyr OS build v3.6.0-5820-gd2a89b3c089e ***
-   Hello World! mt8186_adsp/mt8186_adsp
-
-Debugging
-=========
-
-Given the limited I/O facilities, debugging support remains limited on
-these platforms.  Users with access to hardware-level debug and trace
-tools (e.g. from Cadence) will be able to use them as-is.  Zephyr
-debugging itself is limited to printk/logging techniques at the
-moment.  In theory a bidirectional console like winstream can be used
-with gdb_stub, which has support on Xtensa and via the SDK debuggers,
-but this is still unintegrated.
-
-Toolchains
-**********
-
-The MT8195 toolchain is already part of the Zephyr SDK, so builds for
-the ``mt8195//adsp`` board should work out of the box simply following
-the generic Zephyr build instructions in the Getting Started guide.
-
-The MT8186 toolchain is not, and given the proliferation of Xtensa
-toolchains in the SDK may not be.  The overlay files for the device
-are maintained by the SOF project, however, and building a toolchain
-yourself using crosstools-ng is not difficult or time-consuming.  This
-script should work for most users:
-
-.. code-block:: shell
-
-   #!/bin/sh
-
-   TC=mtk_mt818x_adsp
-
-   # Grab source (these are small)
-   git clone https://github.com/crosstool-ng/crosstool-ng
-   git clone https://github.com/thesofproject/xtensa-overlay
-
-   # Build ct-ng itself
-   cd crosstool-ng
-   ./bootstrap
-   ./configure --enable-local
-   make -j$(nproc)
-
-   mkdir overlays
-   (cd overlays; ln -s ../../xtensa-overlay/xtensa_mt8186.tar.gz xtensa_${TC}.tar.gz)
-
-   # Construct a .config file
-   cat >.config <<EOF
-   CT_CONFIG_VERSION="3"
-   CT_EXPERIMENTAL=y
-   CT_OVERLAY_LOCATION="overlays"
-   CT_OVERLAY_NAME="${TC}"
-   CT_ARCH_XTENSA=y
-   CT_XTENSA_CUSTOM=y
-   CT_TARGET_VENDOR="${TC}_zephyr"
-   CT_TARGET_CFLAGS="-ftls-model=local-exec"
-   CT_CC_GCC_CONFIG_TLS=n
-   CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet"
-   EOF
-
-   # Build
-   ./ct-ng olddefconfig
-   ./ct-ng build.$(nproc)
-
-After this completes, you will find your toolchain in ``~/x-tools``
-and can use it to build by setting it as your Zephyr cross compiler:
-
-.. code-block:: shell
-
-   export CROSS_COMPILE=$HOME/x-tools/xtensa-mtk_mt818x_adsp_zephyr-elf/bin/xtensa-mtk_mt818x_adsp_zephyr-elf-
-   export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile
-
-Closed-source Tools
-===================
-
-Zephyr can also be built by the proprietary Cadence xcc and xt-clang
-toolchains.  Support for those tools is beyond the scope of this
-document, but it works similarly, by specifying your toolchain and
-core identities and paths via the environment, for example:
-
-.. code-block:: shell
-
-   export XTENSA_TOOLS_ROOT=/path/to/XtDevTools
-   export XTENSA_CORE=hifi5_7stg_I64D128
-   export TOOLCHAIN_VER=RI-2021.6-linux
-   export ZEPHYR_TOOLCHAIN_VARIANT=xt-clang
-   export XTENSA_TOOLCHAIN_PATH=$XTENSA_TOOLS_ROOT/install/tools
-   west build -b mt8186_adsp samples/hello_world

boards/mediatek/mt8186/Kconfig.mt8186

@@ -1,5 +0,0 @@
-# Copyright 2024 The ChromiumOS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_MT8186
-	select SOC_MT8186

boards/mediatek/mt8186/board.yml

@@ -1,5 +0,0 @@
-boards:
-  - name: mt8186
-    vendor: mediatek
-    socs:
-      - name: mt8186

boards/mediatek/mt8186/mt8186_adsp.dts

@@ -1,80 +0,0 @@
-/* Copyright 2024 The ChromiumOS Authors
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <mem.h>
-
-/dts-v1/;
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	sram0: memory@4e100000 {
-		 device_type = "memory";
-		 compatible = "mmio-sram";
-		 reg = <0x4e100000 DT_SIZE_K(1024)>;
-	};
-
-	dram0: memory@60000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x60000000 DT_SIZE_M(16)>;
-	};
-
-	dram1: memory@61000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x61000000 DT_SIZE_K(1024)>;
-	};
-
-	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		core_intc: core_intc@0 {
-			compatible = "cdns,xtensa-core-intc";
-			reg = <0 4>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		intc2: intc@10680010 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x10680010 4>;
-			status-reg = <0x10680050>;
-			interrupts = <2 0 0>;
-			mask = <0x3f>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		ostimer64: ostimer64@10683080 {
-			compatible = "mediatek,ostimer64";
-			reg = <0x10683080 28>;
-		};
-
-		ostimer0: ostimer@10683000 {
-			compatible = "mediatek,ostimer";
-			reg = <0x10683000 16>;
-			interrupt-parent = <&core_intc>;
-			interrupts = <18 0 0>;
-		};
-
-		mbox0: mbox@10686100 {
-			compatible = "mediatek,mbox";
-			reg = <0x10686100 16>;
-			interrupt-parent = <&intc2>;
-			interrupts = <1 0 0>;
-		};
-
-		mbox1: mbox@10687100 {
-			compatible = "mediatek,mbox";
-			reg = <0x10687100 16>;
-			interrupt-parent = <&intc2>;
-			interrupts = <2 0 0>;
-		};
-	}; /* soc */
-
-	chosen { };
-	aliases { };
-};

boards/mediatek/mt8188/Kconfig.mt8188

@@ -1,5 +0,0 @@
-# Copyright 2024 The ChromiumOS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_MT8188
-	select SOC_MT8188

boards/mediatek/mt8188/board.yml

@@ -1,5 +0,0 @@
-boards:
-  - name: mt8188
-    vendor: mediatek
-    socs:
-      - name: mt8188

boards/mediatek/mt8188/mt8188_adsp.dts

@@ -1,81 +0,0 @@
-/* Copyright 2024 The ChromiumOS Authors
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <mem.h>
-
-/dts-v1/;
-/ {
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	sram0: memory@4e100000 {
-		 device_type = "memory";
-		 compatible = "mmio-sram";
-		 reg = <0x4e100000 DT_SIZE_K(512)>;
-	};
-
-	dram0: memory@60000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x60000000 DT_SIZE_M(15)>;
-	};
-
-	dram1: memory@61000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x61000000 DT_SIZE_K(1024)>;
-	};
-
-	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		core_intc: core_intc@0 {
-			compatible = "cdns,xtensa-core-intc";
-			reg = <0 4>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		intc2: intc@10b80010 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x10b80010 4>;
-			status-reg = <0x10b80050>;
-			interrupts = <2 0 0>;
-			mask = <0x3f>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		ostimer64: ostimer64@10b83080 {
-			compatible = "mediatek,ostimer64";
-			reg = <0x10b83080 28>;
-		};
-
-		ostimer0: ostimer@10b83000 {
-			compatible = "mediatek,ostimer";
-			reg = <0x10b83000 16>;
-			interrupt-parent = <&core_intc>;
-			interrupts = <18 0 0>;
-		};
-
-		mbox0: mbox@10b86100 {
-			compatible = "mediatek,mbox";
-			reg = <0x10b86100 16>;
-			interrupt-parent = <&intc2>;
-			interrupts = <1 0 0>;
-		};
-
-		mbox1: mbox@10b87100 {
-			compatible = "mediatek,mbox";
-			reg = <0x10b87100 16>;
-			interrupt-parent = <&intc2>;
-			interrupts = <2 0 0>;
-		};
-	}; /* soc */
-
-	chosen { };
-	aliases { };
-};

boards/mediatek/mt8195/mt8195_adsp.dts

@@ -1,94 +0,0 @@
-/* Copyright 2023 The ChromiumOS Authors
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <mem.h>
-
-/dts-v1/;
-/ {
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	sram0: memory@40000000 {
-		 device_type = "memory";
-		 compatible = "mmio-sram";
-		 reg = <0x40000000 DT_SIZE_K(256)>;
-	};
-
-	dram0: memory@60000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x60000000 DT_SIZE_M(17)>;
-	};
-
-	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		cpuclk: cpuclk@10000000 {
-			compatible = "mediatek,mt8195_cpuclk";
-			reg = <0x10000000 380>;
-			cg_reg = <0x10720180>;
-			pll_ctrl_reg = <0x1000c7e0>;
-			freqs_mhz = <26 370 540 720>;
-		};
-
-		core_intc: core_intc@0 {
-			compatible = "cdns,xtensa-core-intc";
-			reg = <0 4>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		intc1: intc@10680130 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x10680130 4>;
-			status-reg = <0x10680150>;
-			interrupts = <1 0 0>;
-			mask = <0x3ffffff0>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		intc23: intc@108030f4 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x108030f4 4>;
-			status-reg = <0x108030fc>;
-			interrupts = <23 0 0>;
-			mask = <0xffff>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		ostimer64: ostimer64@1080d080 {
-			compatible = "mediatek,ostimer64";
-			reg = <0x1080d080 28>;
-		};
-
-		ostimer0: ostimer@1080d000 {
-			compatible = "mediatek,ostimer";
-			reg = <0x1080d000 16>;
-			interrupt-parent = <&intc23>;
-			interrupts = <11 0 0>;
-		};
-
-		mbox0: mbox@10816000 {
-			compatible = "mediatek,mbox";
-			reg = <0x10816000 56>;
-			interrupt-parent = <&intc23>;
-			interrupts = <0 0 0>;
-		};
-
-		mbox1: mbox@10817000 {
-			compatible = "mediatek,mbox";
-			reg = <0x10817000 56>;
-			interrupt-parent = <&intc23>;
-			interrupts = <1 0 0>;
-		};
-	}; /* soc */
-
-	chosen { };
-	aliases { };
-};

boards/mediatek/mt8195_adsp/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MT8195_ADSP
+
+config BOARD
+	default "mt8195_adsp"
+
+endif # BOARD_MT8195_ADSP

boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp

@@ -1,7 +1,7 @@
 # Copyright 2023 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_MT8195
+config BOARD_MT8195_ADSP
-	select SOC_MT8195
+	select SOC_MT8195_ADSP
 	help
 	  Board with Mediatek MT8195 Audio DSP

boards/mediatek/mt8195_adsp/board.yml

@@ -1,6 +1,6 @@
 boards:
-  - name: mt8195
+  - name: mt8195_adsp
     full_name: MT8195 ADSP
     vendor: mediatek
     socs:
-      - name: mt8195
+      - name: mt8195_adsp

boards/mediatek/mt8195_adsp/mt8195_adsp.dts

@@ -0,0 +1,95 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+
+/dts-v1/;
+/ {
+
+#address-cells = <1>;
+#size-cells = <1>;
+
+sram0: memory@40000000 {
+	 device_type = "memory";
+	 compatible = "mmio-sram";
+	 reg = <0x40000000 DT_SIZE_K(256)>;
+};
+
+dram0: memory@60000000 {
+	device_type = "memory";
+	compatible = "mmio-sram";
+	reg = <0x60000000 DT_SIZE_M(17)>;
+};
+
+soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpuclk: cpuclk@10000000 {
+		compatible = "mediatek,mt8195_cpuclk";
+		reg = <0x10000000 380>;
+		cg_reg = <0x10720180>;
+		pll_ctrl_reg = <0x1000c7e0>;
+		freqs_mhz = <26 370 540 720>;
+	};
+
+	core_intc: core_intc@0 {
+		compatible = "cdns,xtensa-core-intc";
+		reg = <0 4>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	intc1: intc@10680130 {
+		compatible = "mediatek,adsp_intc";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x10680130 4>;
+		status-reg = <0x10680150>;
+		interrupts = <1 0 0>;
+		mask = <0x3ffffff0>;
+		interrupt-parent = <&core_intc>;
+	};
+
+	intc23: intc@108030f4 {
+		compatible = "mediatek,adsp_intc";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x108030f4 4>;
+		status-reg = <0x108030fc>;
+		interrupts = <23 0 0>;
+		mask = <0xffff>;
+		interrupt-parent = <&core_intc>;
+	};
+
+	ostimer64: ostimer64@1080d080 {
+		compatible = "mediatek,ostimer64";
+		reg = <0x1080d080 28>;
+	};
+
+	ostimer0: ostimer@1080d000 {
+		compatible = "mediatek,ostimer";
+		reg = <0x1080d000 16>;
+		interrupt-parent = <&intc23>;
+		interrupts = <11 0 0>;
+	};
+
+	mbox0: mbox@10816000 {
+		compatible = "mediatek,mbox";
+		reg = <0x10816000 56>;
+		interrupt-parent = <&intc23>;
+		interrupts = <0 0 0>;
+	};
+
+	mbox1: mbox@10817000 {
+		compatible = "mediatek,mbox";
+		reg = <0x10817000 56>;
+		interrupt-parent = <&intc23>;
+		interrupts = <1 0 0>;
+	};
+}; /* soc */
+
+chosen { };
+aliases { };
+
+};

boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig

@@ -0,0 +1,4 @@
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13000000

boards/mediatek/mt8196/Kconfig.mt8196

@@ -1,5 +0,0 @@
-# Copyright 2024 The ChromiumOS Authors
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_MT8196
-	select SOC_MT8196

boards/mediatek/mt8196/board.yml

@@ -1,5 +0,0 @@
-boards:
-  - name: mt8196
-    vendor: mediatek
-    socs:
-      - name: mt8196

boards/mediatek/mt8196/mt8196_adsp.dts

@@ -1,109 +0,0 @@
-/* Copyright 2024 The ChromiumOS Authors
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <mem.h>
-
-/dts-v1/;
-/ {
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	sram0: memory@4e100000 {
-		 device_type = "memory";
-		 compatible = "mmio-sram";
-		 reg = <0x4e100000 DT_SIZE_K(512)>;
-	};
-
-	dram0: memory@90000000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x90000000 DT_SIZE_M(6)>;
-	};
-
-	dram1: memory@90700000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0x90700000 DT_SIZE_M(1)>;
-	};
-
-	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		core_intc: core_intc@0 {
-			compatible = "cdns,xtensa-core-intc";
-			reg = <0 4>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		/* The 8196 interrupt controller is actually more complicated
-		 * than the driver here supports.  There are 64 total
-		 * interrupt inputs, each of which is a associated with one of
-		 * 16 "groups", each of which is wired to a separate Xtensa
-		 * architectural interrupt. (Whether the mapping of external
-		 * interrupts to groups is mutable is an open question, the
-		 * values here appear to be hardware defaults).  We represent
-		 * each group (strictly each of the high and low 32 interrupts
-		 * of each group) as a separate adsp_intc controller, pointing
-		 * at the same status and enable registers, but with disjoint
-		 * masks.  Note that this disallows configurations where a
-		 * single controller needs to manage interrupts in both the
-		 * high and low 32 bits of the set, but no current drivers
-		 * rely on such a configuration.
-		 */
-
-		intc_g1: intc_g1@1a014010 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x1a014010 4>;
-			status-reg = <0x1a014008>;
-			mask = <0x00007f3f>;
-			interrupts = <1 0 0>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		intc_g2: intc_g2@1a014010 {
-			compatible = "mediatek,adsp_intc";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			reg = <0x1a014010 4>;
-			status-reg = <0x1a014008>;
-			mask = <0x000000c0>;
-			interrupts = <2 0 0>;
-			interrupt-parent = <&core_intc>;
-		};
-
-		ostimer64: ostimer64@1a00b080 {
-			compatible = "mediatek,ostimer64";
-			reg = <0x1a00b080 28>;
-		};
-
-		ostimer0: ostimer@1a00b000 {
-			compatible = "mediatek,ostimer";
-			reg = <0x1a00b000 16>;
-			interrupt-parent = <&intc_g1>;
-			interrupts = <8 0 0>;
-		};
-
-		mbox0: mbox@1a360100 {
-			compatible = "mediatek,mbox";
-			reg = <0x1a360100 16>;
-			interrupt-parent = <&intc_g2>;
-			interrupts = <6 0 0>;
-		};
-
-		mbox1: mbox@1a370100 {
-			compatible = "mediatek,mbox";
-			reg = <0x1a370100 16>;
-			interrupt-parent = <&intc_g2>;
-			interrupts = <7 0 0>;
-		};
-	}; /* soc */
-
-	chosen { };
-	aliases { };
-
-};

boards/mediatek/twister.yaml

@@ -1,18 +0,0 @@
-arch: xtensa
-type: mcu
-toolchain:
-  - xt-clang
-testing:
-  ignore_tags:
-    - net
-    - bluetooth
-    - mcumgr
-variants:
-  mt8195/mt8195/adsp:
-    name: MediaTek MT8195 Audio DSP
-  mt8188/mt8188/adsp:
-    name: MediaTek MT8188 Audio DSP
-  mt8186/mt8186/adsp:
-    name: MediaTek MT8186 Audio DSP
-  mt8196/mt8196/adsp:
-    name: MediaTek MT8196 Audio DSP

boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig

@@ -10,9 +10,11 @@ CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n
 CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
+CONFIG_PINCTRL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
+CONFIG_PINCTRL=y
 
 CONFIG_PM=y

boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig

@@ -9,9 +9,11 @@ CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
 CONFIG_CONSOLE=y
+CONFIG_PINCTRL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
+CONFIG_PINCTRL=y
 
 # power management stuff
 CONFIG_PM=y

boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig

@@ -8,6 +8,7 @@ CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
 CONFIG_GPIO=y
+CONFIG_PINCTRL=y
 CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y

boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig

@@ -8,6 +8,7 @@ CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
 CONFIG_GPIO=y
+CONFIG_PINCTRL=y
 CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y

boards/native/native_sim/Kconfig.defconfig

@@ -32,14 +32,5 @@ config UART_CONSOLE
 
 endif # CONSOLE
 
-# BT relies on PSA Crypto API to perform crypto operations. On this platform
-# this is implemented by Mbed TLS which requires a (possibly true) random
-# number generator to initialize properly. We enable ENTROPY_GENERATOR here
-# instead of manually adding it to all samples/tests configuration files because
-# it looks more compact and easier to maintain.
-config ENTROPY_GENERATOR
-	bool
-	default y if BT
-
 
 endif # BOARD_NATIVE_SIM

boards/native/nrf_bsim/Kconfig.defconfig

@@ -58,19 +58,6 @@ config BT_HCI_IPC
 
 endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP
 
-if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF52_BSIM
-
-# BT relies on PSA Crypto API to perform crypto operations. On this platform
-# this is implemented by Mbed TLS which requires a (possibly true) random
-# number generator to initialize properly. We enable ENTROPY_GENERATOR here
-# instead of manually adding it to all samples/tests configuration files because
-# it looks more compact and easier to maintain.
-config ENTROPY_GENERATOR
-	bool
-	default y if BT
-
-endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF52_BSIM
-
 # The 15.4 driver Tx encryption is currently not functional with this
 # simulated board => we disable it by default. With this Openthread will normally
 # default to encrypt packets on its own.

boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts

@@ -83,10 +83,6 @@
 	};
 };
 
-&uart00 {
-	/delete-property/ clocks;
-};
-
 &uart20 {
 	status = "okay";
 	current-speed = <115200>;

boards/nordic/nrf5340_audio_dk/Kconfig.defconfig

@@ -53,19 +53,6 @@ config FLASH_LOAD_SIZE
 
 endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS
 
-if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP
-
-# BT relies on PSA Crypto API to perform crypto operations. On this platform
-# this is implemented by Mbed TLS which requires a (possibly true) random
-# number generator to initialize properly. We enable ENTROPY_GENERATOR here
-# instead of manually adding it to all samples/tests configuration files because
-# it looks more compact and easier to maintain.
-config ENTROPY_GENERATOR
-	bool
-	default y if BT
-
-endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP
-
 config BT_HCI_IPC
 	default y if BT
 

boards/nordic/nrf5340dk/Kconfig.defconfig

@@ -43,19 +43,6 @@ config SRAM_SIZE
 
 endif # BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
 
-if BOARD_NRF5340DK_NRF5340_CPUAPP
-
-# BT relies on PSA Crypto API to perform crypto operations. On this platform
-# this is implemented by Mbed TLS which requires a (possibly true) random
-# number generator to initialize properly. We enable ENTROPY_GENERATOR here
-# instead of manually adding it to all samples/tests configuration files because
-# it looks more compact and easier to maintain.
-config ENTROPY_GENERATOR
-	bool
-	default y if BT
-
-endif # BOARD_NRF5340DK_NRF5340_CPUAPP
-
 if BOARD_NRF5340DK_NRF5340_CPUAPP_NS
 
 config FLASH_LOAD_OFFSET

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -27,7 +27,7 @@
 
 		cpuapp_ram0x_region: memory@2f011000 {
 			compatible = "nordic,owned-memory";
-			reg = <0x2f011000 DT_SIZE_K(260)>;
+			reg = <0x2f010000 DT_SIZE_K(260)>;
 			status = "disabled";
 			nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
 			#address-cells = <1>;
@@ -185,8 +185,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpurad_slot0_partition: partition@54000 {
+		cpurad_slot0_partition: partition@66000 {
-			reg = <0x54000 DT_SIZE_K(256)>;
+			reg = <0x66000 DT_SIZE_K(256)>;
 		};
 	};
 
@@ -197,8 +197,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpuapp_slot0_partition: partition@94000 {
+		cpuapp_slot0_partition: partition@a6000 {
-			reg = <0x94000 DT_SIZE_K(320)>;
+			reg = <0xa6000 DT_SIZE_K(248)>;
 		};
 
 		cpuppr_code_partition: partition@e4000 {
@@ -222,7 +222,7 @@
 		};
 
 		storage_partition: partition@1e3000 {
-			reg = < 0x1e3000 DT_SIZE_K(40) >;
+			reg = < 0x1e3000 DT_SIZE_K(24) >;
 		};
 	};
 };

boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi

@@ -13,7 +13,6 @@
 				<LPUART0_TXD_P0_3>;
 			drive-strength = "low";
 			slew-rate = "fast";
-			input-enable;
 		};
 	};
 

boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi

@@ -140,18 +140,18 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x00000000 DT_SIZE_K(80)>;
+			reg = <0x00000000 DT_SIZE_K(64)>;
 		};
 		/* For the MCUBoot "upgrade only" method,
 		 * the slot sizes must be equal.
 		 */
-		slot0_partition: partition@14000 {
+		slot0_partition: partition@10000 {
 			label = "image-0";
-			reg = <0x00014000 DT_SIZE_K(984)>;
+			reg = <0x00010000 DT_SIZE_K(992)>;
 		};
-		slot1_partition: partition@10A000 {
+		slot1_partition: partition@108000 {
 			label = "image-1";
-			reg = <0x0010A000 DT_SIZE_K(984)>;
+			reg = <0x00108000 DT_SIZE_K(992)>;
 		};
 		/* storage_partition is placed in WINBOND flash memory*/
 	};

boards/nxp/frdm_rw612/frdm_rw612.dts

@@ -73,32 +73,6 @@
 		erase-block-size = <4096>;
 		write-block-size = <1>;
 		spi-max-frequency = <104000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			boot_partition: partition@0 {
-				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
-			};
-			/* The MCUBoot swap-move algorithm uses the last 2 sectors
-			 * of the primary slot0 for swap status and move.
-			 */
-			slot0_partition: partition@20000 {
-				label = "image-0";
-				reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>;
-			};
-			slot1_partition: partition@323000 {
-				label = "image-1";
-				reg = <0x00323000 DT_SIZE_M(3)>;
-			};
-			storage_partition: partition@623000 {
-				label = "storage";
-				reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>;
-			};
-		};
 	};
 	aps6404l: aps6404l@2 {
 			compatible = "nxp,imx-flexspi-aps6404l";

boards/nxp/s32z2xxdc2/Kconfig.defconfig

@@ -30,20 +30,4 @@ config NET_L2_ETHERNET
 
 endif # NETWORKING
 
-if XIP
-# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded
-# over AXIM interface
-config BUILD_OUTPUT_ADJUST_LMA
-	default "-0x47800000"
-
-config CPU_CORTEX_R52_CACHE_SEGREGATION
-	default y
-
-config CPU_CORTEX_R52_ICACHE_FLASH_WAY
-	default 4
-
-config CPU_CORTEX_R52_DCACHE_FLASH_WAY
-	default 1
-endif # XIP
-
 endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts

@@ -13,8 +13,7 @@
 	compatible = "nxp,s32z270";
 
 	chosen {
-		zephyr,sram = &dram0;
+		zephyr,sram = &sram0;
-		zephyr,flash = &cram0;
 		zephyr,canbus = &canxl0;
 	};
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig

@@ -1,7 +1,7 @@
 # Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_XIP=y
+CONFIG_XIP=n
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts

@@ -13,8 +13,9 @@
 	compatible = "nxp,s32z270";
 
 	chosen {
-		zephyr,sram = &dram1;
+		zephyr,sram = &sram1;
-		zephyr,flash = &cram1;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
 		zephyr,canbus = &flexcan0;
 	};
 

boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig

@@ -1,7 +1,7 @@
 # Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_XIP=y
+CONFIG_XIP=n
 CONFIG_ISR_STACK_SIZE=512
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000

boards/nxp/s32z2xxdc2/support/startup.cmm

@@ -20,17 +20,20 @@
 ;                  - Core0 and Core2 (redundancy) operate as a lockstep pair   *
 ;                  - Core1 and Core3 (redundancy) operate as a lockstep pair   *
 ;                 default: yes                                                 *
+;   - thumb       set to "yes" to select the T32 instruction set at reset      *
+;                 default: no                                                 *
 ;                                                                              *
 ;*******************************************************************************
 
 ENTRY %LINE &args
-LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit
+LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit
 
 &command=STRing.SCANAndExtract("&args","command=","debug")
 &elfFile=STRing.SCANAndExtract("&args","elfFile=","")
 &rtu=STRing.SCANAndExtract("&args","rtu=","0")
 &core=STRing.SCANAndExtract("&args","core=","0")
 &lockstep=STRing.SCANAndExtract("&args","lockstep=","yes")
+&thumb=STRing.SCANAndExtract("&args","thumb=","no")
 
 IF ("&elfFile"=="")
 (
@@ -56,6 +59,12 @@ IF (&core<0||&core>3)
   ENDDO
 )
 
+; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit)
+IF ("&thumb"=="yes")
+  &thumbBit="1"
+ELSE
+  &thumbBit="0"
+
 ; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit)
 IF ("&lockstep"=="yes")
   &spltLckBit="0"
@@ -117,8 +126,8 @@ GOSUB EnableRTU1
 ; Init RTU SRAM
 DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm
 
-; Set reset value for split-lock mode
+; Set reset value for TE bit and split-lock mode
-Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit)  ; CFG_CORE
+Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit)  ; CFG_CORE
 
 ; Write loop to self instruction
 Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF

boards/qemu/cortex_m3/Kconfig.defconfig

@@ -12,12 +12,4 @@ choice NULL_POINTER_EXCEPTION_DETECTION
 	default NULL_POINTER_EXCEPTION_DETECTION_NONE
 endchoice
 
-# BT relies on PSA Crypto API to perform crypto operations and, on this platform,
-# these APIs are provided thougth Mbed TLS. Unfortunately this platform is not
-# provided with a true random number generator which is required to properly
-# initialize the PSA Crypto core, so we need to enable the fake TEST_RANDOM_GENERATOR.
-config TEST_RANDOM_GENERATOR
-	bool
-	default y if BT
-
 endif # BOARD_QEMU_CORTEX_M3

boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3

@@ -2,4 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_XIAO_ESP32C3
-	select SOC_ESP32C3_FN4
+	select SOC_ESP32C3_FX4

boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay

@@ -15,12 +15,5 @@
 
 	bt_hci_uart: bt_hci_uart {
 		compatible = "zephyr,bt-hci-uart";
-		status = "okay";
-
-		da1453x {
-			compatible = "renesas,bt-hci-da1453x";
-			reset-gpios = <&mikrobus_header 1 GPIO_ACTIVE_HIGH>;
-			status = "okay";
-		};
 	};
 };

boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts

@@ -24,7 +24,6 @@
 		zephyr,console = &usart0;
 		zephyr,flash = &flash0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 	};
 

boards/silabs/dev_kits/sltb004a/sltb004a.dts

@@ -27,7 +27,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 	};

boards/silabs/dev_kits/sltb009a/sltb009a.dts

@@ -16,7 +16,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 	};

boards/silabs/dev_kits/sltb010a/Kconfig.defconfig

@@ -26,9 +26,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 config REGULATOR

boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2024 Silicon Laboratories Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <dt-bindings/pinctrl/silabs/xg22-pinctrl.h>
-
-&pinctrl {
-	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
-			drive-push-pull;
-			output-high;
-		};
-		group1 {
-			pins = <USART0_RX_PC1>;
-			input-enable;
-		};
-	};
-
-	usart1_default: usart1_default {
-		group0 {
-			pins = <USART1_TX_PA5>;
-			drive-push-pull;
-			output-high;
-		};
-		group1 {
-			pins = <USART1_RX_PA6>;
-			input-enable;
-			silabs,input-filter;
-		};
-	};
-
-	i2c0_default: i2c0_default {
-		group0 {
-			pins = <I2C0_SDA_PD2>, <I2C0_SCL_PD3>;
-			drive-open-drain;
-			bias-pull-up;
-		};
-	};
-};

boards/silabs/dev_kits/sltb010a/sltb010a.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include <silabs/efr32bg22.dtsi>
-#include "sltb010a-pinctrl.dtsi"
+#include <silabs/efr32bg2x-pinctrl.dtsi>
 #include "thunderboard.dtsi"
 #include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
 
@@ -102,7 +102,7 @@
 };
 
 &sw_imu_enable {
-	enable-gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 };
 
 &bt_hci_silabs {

boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay

@@ -11,9 +11,9 @@
 };
 
 &sw_sensor_enable {
-	enable-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 };
 
 &sw_mic_enable {
-	enable-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioa GECKO_PIN(0) GPIO_ACTIVE_HIGH>;
 };

boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay

@@ -12,17 +12,17 @@
 };
 
 &button0 {
-	gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
+	gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>;
 };
 
 &led0 {
-	gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
+	gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 };
 
 &sw_sensor_enable {
-	enable-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>;
 };
 
 &sw_mic_enable {
-	enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>;
 };

boards/silabs/dev_kits/sltb010a/sltb010a_defconfig

@@ -8,3 +8,4 @@ CONFIG_GPIO=y
 CONFIG_SOC_GECKO_EMU_DCDC=y
 CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y

boards/silabs/dev_kits/sltb010a/thunderboard.dtsi

@@ -5,13 +5,13 @@
  */
 
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <silabs/gpio_gecko.h>
 
 / {
 	chosen {
 		zephyr,bt-c2h-uart = &usart1;
 		zephyr,console = &usart1;
 		zephyr,shell-uart = &usart1;
-		zephyr,uart-pipe = &usart1;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 	};
@@ -19,7 +19,7 @@
 	leds {
 		compatible = "gpio-leds";
 		led0: led_0 {
-			gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>;
 			label = "LED 0";
 		};
 	};
@@ -27,7 +27,7 @@
 	buttons {
 		compatible = "gpio-keys";
 		button0: button_0 {
-			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>;
 			label = "User Push Button 0";
 			zephyr,code = <INPUT_KEY_0>;
 		};
@@ -35,7 +35,7 @@
 
 	wake_up_trigger: gpio-wake-up  {
 		compatible = "silabs,gecko-wake-up-trigger";
-		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>;
 	};
 
 	/* GPIOs that power up different sensors */
@@ -138,6 +138,17 @@
 	status = "okay";
 };
 
+&pinctrl {
+	i2c0_default: i2c0_default {
+		group1 {
+			psels = <GECKO_PSEL(I2C_SDA, D, 2)>,
+				<GECKO_PSEL(I2C_SCL, D, 3)>,
+				<GECKO_LOC(I2C_SDA, 3)>,
+				<GECKO_LOC(I2C_SCL, 3)>;
+		};
+	};
+};
+
 &i2c0 {
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";

boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig

@@ -31,9 +31,6 @@ config COMMON_LIBC_MALLOC_ARENA_SIZE
 config MAIN_STACK_SIZE
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 if SHELL
 
 config SHELL_STACK_SIZE

boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2024 Silicon Laboratories Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
-
-&pinctrl {
-	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PA5>;
-			drive-push-pull;
-			output-high;
-		};
-		group1 {
-			pins = <USART0_RX_PA6>;
-			input-enable;
-			silabs,input-filter;
-		};
-	};
-
-	i2c0_default: i2c0_default {
-		group0 {
-			pins = <I2C0_SCL_PC4>, <I2C0_SDA_PC5>;
-			drive-open-drain;
-			bias-pull-up;
-		};
-	};
-};

boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts

@@ -6,9 +6,9 @@
 
 /dts-v1/;
 #include <silabs/efr32mg24b310f1536im48.dtsi>
+#include <silabs/efr32mg24-pinctrl.dtsi>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
-#include "xg24_dk2601b-pinctrl.dtsi"
 
 / {
 	model = "Silicon Labs BRD2601B (xG24 Dev Kit)";
@@ -17,7 +17,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
@@ -36,37 +35,37 @@
 	leds {
 		compatible = "gpio-leds";
 		red_led: led_2 {
-			gpios = <&gpiod 2 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiod GECKO_PIN(2) GPIO_ACTIVE_LOW>;
 		};
 		green_led: led_0 {
-			gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+			gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_LOW>;
 		};
 		blue_led: led_1 {
-			gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_LOW>;
 		};
 	};
 
 	buttons {
 		compatible = "gpio-keys";
 		button0: button_0 {
-			gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_LOW>;
 			zephyr,code = <INPUT_KEY_0>;
 		};
 		button1: button_1 {
-			gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>;
 			zephyr,code = <INPUT_KEY_1>;
 		};
 	};
 
 	wake_up_trigger: gpio-wake-up  {
 		compatible = "silabs,gecko-wake-up-trigger";
-		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>;
 	};
 
 	sensor_enable: gpio_switch_0 {
 		compatible = "regulator-fixed";
 		regulator-name = "sensor_enable";
-		enable-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
+		enable-gpios = <&gpioc GECKO_PIN(9) GPIO_ACTIVE_HIGH>;
 		regulator-boot-on;
 	};
 };

boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig

@@ -7,6 +7,7 @@ CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y
 CONFIG_REGULATOR=y
 CONFIG_SOC_GECKO_EMU_DCDC=y
 CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y

boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig

@@ -26,9 +26,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 config REGULATOR

boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi

@@ -5,13 +5,13 @@
  */
 
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <silabs/gpio_gecko.h>
 
 / {
 	chosen {
 		zephyr,bt-c2h-uart = &usart1;
 		zephyr,console = &usart1;
 		zephyr,shell-uart = &usart1;
-		zephyr,uart-pipe = &usart1;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 	};
@@ -19,7 +19,7 @@
 	leds {
 		compatible = "gpio-leds";
 		led0: led_0 {
-			gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>;
 			label = "LED 0";
 		};
 	};
@@ -27,7 +27,7 @@
 	buttons {
 		compatible = "gpio-keys";
 		button0: button_0 {
-			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>;
 			label = "User Push Button 0";
 			zephyr,code = <INPUT_KEY_0>;
 		};
@@ -35,7 +35,7 @@
 
 	wake_up_trigger: gpio-wake-up  {
 		compatible = "silabs,gecko-wake-up-trigger";
-		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>;
 	};
 
 	/* GPIOs that power up different sensors */
@@ -138,6 +138,17 @@
 	status = "okay";
 };
 
+&pinctrl {
+	i2c0_default: i2c0_default {
+		group1 {
+			psels = <GECKO_PSEL(I2C_SDA, D, 2)>,
+				<GECKO_PSEL(I2C_SCL, D, 3)>,
+				<GECKO_LOC(I2C_SDA, 3)>,
+				<GECKO_LOC(I2C_SCL, 3)>;
+		};
+	};
+};
+
 &i2c0 {
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";

boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2024 Silicon Laboratories Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <dt-bindings/pinctrl/silabs/xg27-pinctrl.h>
-
-&pinctrl {
-	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PC0>, <USART0_CLK_PC2>;
-			drive-push-pull;
-			output-high;
-		};
-		group1 {
-			pins = <USART0_RX_PC1>;
-			input-enable;
-		};
-	};
-
-	usart1_default: usart1_default {
-		group0 {
-			pins = <USART1_TX_PA5>;
-			drive-push-pull;
-			output-high;
-		};
-		group1 {
-			pins = <USART1_RX_PA6>;
-			input-enable;
-			silabs,input-filter;
-		};
-	};
-
-	i2c0_default: i2c0_default {
-		group0 {
-			pins = <I2C0_SDA_PD2>, <I2C0_SCL_PD3>;
-			drive-open-drain;
-			bias-pull-up;
-		};
-	};
-};

boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include <silabs/efr32bg27.dtsi>
-#include "xg27_dk2602a-pinctrl.dtsi"
+#include <silabs/efr32bg2x-pinctrl.dtsi>
 #include "thunderboard.dtsi"
 #include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
 
@@ -106,25 +106,25 @@
 };
 
 &led0 {
-	gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
+	gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 };
 
 &sw_sensor_enable {
-	enable-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>;
 };
 
 
 &sw_mic_enable {
-	enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>;
 };
 
 
 &sw_imu_enable {
-	enable-gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
+	enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 };
 
 &button0 {
-	gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
+	gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>;
 };
 
 &bt_hci_silabs {

boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig

@@ -8,3 +8,4 @@ CONFIG_GPIO=y
 CONFIG_SOC_GECKO_EMU_DCDC=y
 CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y

boards/silabs/radio_boards/common/efr32-series1-common.dtsi

@@ -11,7 +11,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;

boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4104A

boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4161A

boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4170A

boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4180A

boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi

@@ -1,23 +1,18 @@
 /*
  * Copyright (c) 2023 Antmicro <www.antmicro.com>
- * Copyright (c) 2024 Silicon Laboratories Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <dt-bindings/pinctrl/silabs/xg21-pinctrl.h>
+#include <arm/silabs/gpio_gecko.h>
+#include <dt-bindings/pinctrl/gecko-pinctrl.h>
 
 &pinctrl {
 	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PA5>;
-			drive-push-pull;
-			output-high;
-		};
 		group1 {
-			pins = <USART0_RX_PA6>;
+			psels = <GECKO_PSEL(UART_TX, A, 5)>,
-			input-enable;
+				<GECKO_PSEL(UART_RX, A, 6)>,
-			silabs,input-filter;
+				<GECKO_LOC(UART, 0)>;
 		};
 	};
 };

boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts

@@ -16,7 +16,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;

boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig

@@ -5,3 +5,4 @@ CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
+CONFIG_PINCTRL=y

boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4250B

boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_SLWRB4255A

boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts

@@ -18,7 +18,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 	};

boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig

@@ -37,9 +37,6 @@ config MAIN_STACK_SIZE
 	default 3072 if PM
 	default 2304
 
-config BT_SEND_ECC_EMULATION
-	default y
-
 endif # BT
 
 endif # BOARD_XG24_RB4187C

boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi

@@ -4,19 +4,15 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+#include <arm/silabs/gpio_gecko.h>
+#include <dt-bindings/pinctrl/gecko-pinctrl.h>
 
 &pinctrl {
 	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PA8>;
-			drive-push-pull;
-			output-high;
-		};
 		group1 {
-			pins = <USART0_RX_PA9>;
+			psels = <GECKO_PSEL(UART_TX, A, 8)>,
-			input-enable;
+				<GECKO_PSEL(UART_RX, A, 9)>,
-			silabs,input-filter;
+				<GECKO_LOC(UART, 0)>;
 		};
 	};
 };

boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts

@@ -17,7 +17,6 @@
 	chosen {
 		zephyr,console = &usart0;
 		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
@@ -36,11 +35,11 @@
 	leds {
 		compatible = "gpio-leds";
 		led0: led_0 {
-			gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>;
 			label = "LED 0";
 		};
 		led1: led_1 {
-			gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
 			label = "LED 1";
 		};
 	};
@@ -48,12 +47,12 @@
 	buttons {
 		compatible = "gpio-keys";
 		button0: button_0 {
-			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>;
 			label = "User Push Button 0";
 			zephyr,code = <INPUT_KEY_0>;
 		};
 		button1: button_1 {
-			gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
+			gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>;
 			label = "User Push Button 1";
 			zephyr,code = <INPUT_KEY_1>;
 		};

boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig

@@ -7,3 +7,4 @@ CONFIG_SERIAL=y
 CONFIG_GPIO=y
 CONFIG_SOC_GECKO_EMU_DCDC=y
 CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
+CONFIG_PINCTRL=y

boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi

@@ -5,40 +5,34 @@
  */
 
 #include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+#include <dt-bindings/pinctrl/gecko-pinctrl.h>
 
 &pinctrl {
 	/* configuration for uart0 device, default state */
 	usart0_default: usart0_default {
-		group0 {
-			pins = <USART0_TX_PA5>;
-			drive-push-pull;
-			output-high;
-		};
 		group1 {
-			pins = <USART0_RX_PA6>;
+			/* configure PA.6 as UART_RX and PA.5 as UART_TX */
-			input-enable;
+			psels = <GECKO_PSEL(UART_TX, A, 5)>,
-			silabs,input-filter;
+				<GECKO_PSEL(UART_RX, A, 6)>,
+				<GECKO_LOC(UART, 0)>;
 		};
 	};
 
 	eusart1_default: eusart1_default {
-		group0 {
-			pins = <EUSART1_TX_PC6>, <EUSART1_SCLK_PC2>, <EUSART1_CS_PA7>;
-			drive-push-pull;
-			output-high;
-		};
 		group1 {
-			pins = <EUSART1_RX_PC3>;
+			psels = <GECKO_PSEL(SPI_SCK, C, 2)>,
-			input-enable;
+				<GECKO_PSEL(SPI_MISO, C, 3)>,
+				<GECKO_PSEL(SPI_MOSI, C, 6)>,
+				<GECKO_PSEL(SPI_CSN, A, 7)>;
 		};
 	};
 
 	i2c0_default: i2c0_default {
-		group0 {
+		group1 {
-			pins = <I2C0_SDA_PB3>, <I2C0_SCL_PB4>;
+			psels = <GECKO_PSEL(I2C_SDA, B, 3)>,
-			drive-open-drain;
+				<GECKO_PSEL(I2C_SCL, B, 4)>,
-			bias-pull-up;
+				<GECKO_LOC(I2C_SDA, 5)>,
+				<GECKO_LOC(I2C_SCL, 5)>;
 		};
 	};
 

boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts

@@ -33,14 +33,14 @@
 	leds {
 		compatible = "gpio-leds";
 		blue_led: led_1 {
-			gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+			gpios = <&gpioa GECKO_PIN(8) GPIO_ACTIVE_LOW>;
 		};
 
 	};
 
 	wake_up_trigger: gpio-wake-up  {
 		compatible = "silabs,gecko-wake-up-trigger";
-		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>;
 	};
 
 };