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8 changed files with 152 additions and 0 deletions

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@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_AMBIQ wdt_ambiq.c)
zephyr_library_sources_ifdef(CONFIG_WDT_XMC4XXX wdt_xmc4xxx.c)
zephyr_library_sources_ifdef(CONFIG_WWDT_NUMAKER wdt_wwdt_numaker.c)
zephyr_library_sources_ifdef(CONFIG_WDT_ENE_KB1200 wdt_ene_kb1200.c)
zephyr_library_sources_ifdef(CONFIG_WDT_IWDG_CH32V00X wdt_iwdg_ch32v00x.c)
zephyr_library_sources_ifdef(CONFIG_WDT_DW wdt_dw.c wdt_dw_common.c)
zephyr_library_sources_ifdef(CONFIG_WDT_INTEL_ADSP wdt_intel_adsp.c wdt_dw_common.c)

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@ -134,4 +134,6 @@ source "drivers/watchdog/Kconfig.ene"
source "drivers/watchdog/Kconfig.litex"
source "drivers/watchdog/Kconfig.ch32v00x"
endif # WATCHDOG

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@ -0,0 +1,9 @@
# Copyright (c) 2024 Google LLC.
# SPDX-License-Identifier: Apache-2.0
config WDT_IWDG_CH32V00X
bool "CH32V00x Independent Watchdog (IWDG) driver"
default y
depends on DT_HAS_WCH_IWDG_ENABLED
help
Enable the Independent Watchdog (IWDG) driver for CH32V00x SOCs.

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@ -0,0 +1,92 @@
/*
* Copyright (c) 2024 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_iwdg
#include <zephyr/drivers/watchdog.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <errno.h>
#include <ch32_iwdg.h>
static int iwdg_ch32v00x_setup(const struct device *dev, uint8_t options)
{
if (options != 0) {
return -ENOTSUP;
}
IWDG->CTLR = CTLR_KEY_Enable;
return 0;
}
static int iwdg_ch32v00x_disable(const struct device *dev)
{
return -EPERM;
}
static int iwdg_ch32v00x_install_timeout(const struct device *dev,
const struct wdt_timeout_cfg *config)
{
/* The IWDT is driven by the 128 kHz LSI oscillator with at least a /4 prescaler. */
int prescaler = 0;
uint32_t reload = config->window.max * (128 / 4);
if (config->callback != NULL) {
return -ENOTSUP;
}
if (config->window.min != 0) {
return -ENOTSUP;
}
if ((config->flags & WDT_FLAG_RESET_MASK) != WDT_FLAG_RESET_CPU_CORE) {
return -ENOTSUP;
}
for (; reload > IWDG_RL && prescaler < IWDG_PR;) {
prescaler++;
reload /= 2;
}
/* The highest prescaler is effectively invalid. Use that to detect a too long timeout. */
if (prescaler == IWDG_PR) {
return -EINVAL;
}
/* Wait for the watchdog to be idle, unlock it, update, and wait for idle. */
while ((IWDG->STATR & (IWDG_RVU | IWDG_PVU)) != 0) {
}
IWDG->CTLR = IWDG_WriteAccess_Enable;
IWDG->PSCR = prescaler;
IWDG->RLDR = reload;
while ((IWDG->STATR & (IWDG_RVU | IWDG_PVU)) != 0) {
}
return 0;
}
static int iwdg_ch32v00x_feed(const struct device *dev, int channel_id)
{
IWDG->CTLR = CTLR_KEY_Reload;
return 0;
}
static const struct wdt_driver_api iwdg_ch32v00x_api = {
.setup = iwdg_ch32v00x_setup,
.disable = iwdg_ch32v00x_disable,
.install_timeout = iwdg_ch32v00x_install_timeout,
.feed = iwdg_ch32v00x_feed,
};
static int iwdg_ch32v00x_init(const struct device *dev)
{
return 0;
}
DEVICE_DT_INST_DEFINE(0, iwdg_ch32v00x_init, NULL, NULL, NULL, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &iwdg_ch32v00x_api);

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@ -0,0 +1,12 @@
# Copyright (c) 2024 Google LLC.
# SPDX-License-Identifier: Apache-2.0
description: CH32V00x Independent Watchdog (IWDG)
compatible: "wch,iwdg"
include: base.yaml
properties:
reg:
required: true

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@ -94,6 +94,11 @@
interrupts = <12>;
};
iwdg: watchdog@40003000 {
compatible = "wch,iwdg";
reg = <0x40003000 16>;
};
pwr: pwr@40007000 {
compatible = "wch,pwr";
reg = <0x40007000 16>;

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@ -0,0 +1,16 @@
/*
* Copyright (c) 2024 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _CH32_IWDG_H
#define _CH32_IWDG_H
#ifdef CONFIG_SOC_CH32V003
#include <ch32v003fun.h>
#else
#error "SoC not supported!"
#endif
#endif

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@ -0,0 +1,15 @@
/*
* Copyright (c) 2024 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
aliases {
watchdog0 = &iwdg;
};
};
&iwdg {
status = "okay";
};