Commit graph

136,983 commits

Author SHA1 Message Date
Khoa Tran
dc1d5dba0b samples: drivers: uart: Add support samples for SAU UART driver
Add devicetree .overlay to support sample apps for Renesas RA
SAU UART drivers:
- samples/drivers/uart/passthrough

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
44c74fa002 boards: renesas: ra: Add SAU UART node for Renesas RA0 boards
Add SAU UART device tree node for Renesas RA0 boards

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
7ad20b9997 dts: arm: renesas: Add SAU UART devicetree node for Renesas RA0
Add SAU UART devicetree node support for Renesas RA0 series SoCs

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
dc4e092830 drivers: serial: Initial SAU UART driver support for Renesas RA0 series
Initial SAU UART driver support for Renesas RA0 series

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
1df9afc2f3 boards: renesas: ra: Add support for Renesas fpb_ra0e1 board
Add support for Renesas RA fpb_ra0e1 board

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
75b14349ce dts: arm: renesas: ra: Add support for Renesas RA0E1 SoCs
Add devicetree support for Renesas RA0E1 SoCs

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
dead85721b drivers: misc: Update interrupt handling for ext-int to support RA0
Update interrupt handling for renesas_ra_external_interrupt
to support RA0

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
cd95e8e5a5 drivers: flash: Update interrupt number assign to support RA0
Update interrupt number assign for soc_flash_lp to support RA0

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
6f65b1ac5e soc: renesas: ra: Add config to indicate the SoC support int feature
Add config SOC_RA_DYNAMIC_INTERRUPT_NUMBER to indicate the SoC
support the dynamic interrupt number assignment feature.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
f83f6d3403 soc: renesas: ra: Add support for Renesas RA0E1 SoCs
Add support for Renesas RA0E1 SoCs

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
05b1e0ee7a drivers: clock_control: Add support for Renesas RA0 SoCs
Add Clock Control driver support for Renesas RA0 SoCs

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
56fd42de76 include: zephyr: Update the doxygen for renesas_ra_cgc
Update the Doxygen for renesas_ra_cgc since some lines exceed
the maximum length.

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
ee99677faa drivers: gpio: Update Renesas RA GPIO driver to support RA0 series
- Update Renesas RA GPIO driver to support Renesas RA0 series
- Add macro to disable port external interrupt the the compatible
nodes `renesas,ra-external-interrupt` are not enabled.

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Tran
1c67a64bff drivers: pinctrl: Add support for Renesas RA0 SoCs
Add pinctrl driver support for Renesas RA0 SoCs

Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Khoa Nguyen
3b3ab35c54 manifest: Update revision for hal_renesas
Update revision for hal_renesas to get the RA0E1
and SAU_UART support

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2026-03-02 10:48:45 +01:00
Muhammed Asif
3a84ecb6b8 tests: drivers: counter: Adds sam_e54 test support files
Added sam_e54_xpro.overlay files for rtc
Added sam_e54_xpro platform allow in testcase.yaml.
Added board support in main.c
Added an extra scenario to testcase.yaml

Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
2026-03-02 10:47:37 +01:00
Muhammed Asif
3096cae23f drivers: counter: microchip: Add support for counter using rtc
- Adds the necessary support for counter using rtc peripheral.

Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
2026-03-02 10:47:37 +01:00
Muhammed Asif
830368bee2 dts: bindings: microchip: counter with rtc g1 binding
- Adds the binding for counter with rtc peripheral for g1 driver.

Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
2026-03-02 10:47:37 +01:00
Hieu Nguyen
183a2eca3c samples: drivers: counter: Add support for RZ devices
Add sample support for Counter driver of:
- RZ/T2L-RSK
- RZ/G2L-SMARC, RZ/G2LC-SMARC, RZ/G2UL-SMARC
- RZ/V2N-EVK, RZ/V2H-EVK

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2026-03-02 10:46:47 +01:00
Hieu Nguyen
8d84fc8b4a tests: drivers: counter: Add support for RZ devices
Add test support for Counter driver of:
- RZ/T2L-RSK
- RZ/G2L-SMARC, RZ/G2LC-SMARC, RZ/G2UL-SMARC
- RZ/V2N-EVK, RZ/V2H-EVK

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2026-03-02 10:46:47 +01:00
Hieu Nguyen
0d7d5e7fe9 boards: renesas: Add Counter support for RZ devices
Add Counter support for:
- RZ/T2L-RSK
- RZ/G2L-SMARC, RZ/G2LC-SMARC, RZ/G2UL-SMARC
- RZ/V2N-EVK, RZ/V2H-EVK

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2026-03-02 10:46:47 +01:00
Hieu Nguyen
f4ce40c8b6 drivers: counter: Update driver for RZ devices
Reduce the complexity of the set-alarm and set-top functions.
Improve the error handling.
Replace IRQ macros with static inline functions to centralize GIC/NVIC
conditional handling.

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2026-03-02 10:46:47 +01:00
Hieu Nguyen
af9cf45354 dts: renesas: Add Counter support for RZ SoCs
Add GTM nodes for devicetree of
- RZ/T2L
- RZ/G2UL, RZ/G2L, RZ/G2LC
- RZ/V2H R8 Core, RZ/V2H M33 Core, RZ/V2N

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2026-03-02 10:46:47 +01:00
Damian Krolik
02191db6fe boards: enable BT_HCI_IPC by default only if BT_HCI
Boards based on Nordic Semiconductor's nRF53 and nRF54H
series enable the Bluetooth HCI IPC driver whenever BT is
set, even though the original BT_HCI_IPC symbol depends
also on BT_HCI.

Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
2026-02-28 21:13:43 +01:00
Stephan Linz
34bbc32697 boards: shields: mikroe_mcp25625_click: add missing STBY on CAN transceiver
Without the special CAN transceiver node to the MCP25625 Click, the STBY
pin will be pulled high from the internal pull-up resistor in the MCP2562
CAN transceiver, causing the CAN transceiver to stay in stand-by mode,
preventing any CAN bus traffic from taking place.

Signed-off-by: Stephan Linz <linz@li-pro.net>
2026-02-28 21:13:19 +01:00
Stephan Linz
045eaf472d boards: shields: mikroe_mcp251x_click: rearrange dts and use macros
Rearrange the devicetree overlays for the MikroElektronika MCP251x
shields to better align with node and property order used in the
rest of the tree.

Use "can" as devicetree node name as recommended in the Devicetree
specification.

Signed-off-by: Stephan Linz <linz@li-pro.net>
2026-02-28 21:13:19 +01:00
Jeppe Odgaard
5fba04f153 include: led_strip: improve api documentation
Not all callbacks are mandatory.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2026-02-28 21:13:05 +01:00
Jeppe Odgaard
ea6dfedfe4 drivers: led_strip: ws2812_i2c: add update_channels
Add support for LED strip update channels.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2026-02-28 21:13:05 +01:00
Jeppe Odgaard
8edafa9e28 drivers: led_strip: ws2812_i2c: refactor update_rgb
Move the non-RGB mapping code into an update function.
This creates simpler functions and makes implementation of LED strip API's
update_channels function simpler.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2026-02-28 21:13:05 +01:00
Arunprasath P
c41470a200 tests: drivers: dma: Enable twister tests for pic32cm_jh01_cpro board
Add pic32cm_jh01_cpro.overlay files to the chan_blen_transfer
and loop_transfer test projects to enable DMA twister
testing on this board.

Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
2026-02-28 21:12:52 +01:00
Arunprasath P
ca883dedef boards: microchip: pic32cm_jh01_cpro: Add DMA to supported list
Update pic32cm_jh01_cpro.yml to include DMA in the supported
features list.
Also enable the DMA controller node in pic32cm_jh01_cpro.dts.

Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
2026-02-28 21:12:52 +01:00
Arunprasath P
f7018c171d drivers: dma: microchip: g2: Introduce DMA G2 driver
Add G2 DMA driver for Microchip DMAC Peripherals.
Implement the Zephyr DMA driver APIs, including channel configuration,
start, stop, suspend, and resume operations.

Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
2026-02-28 21:12:52 +01:00
Arunprasath P
01642918a9 soc: microchip: pic32cm_jh: add DT helper file
Add DT helper file for PIC32CM-JH family devices to support
SoC-specific device tree definitions and utilities.

Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
2026-02-28 21:12:52 +01:00
Arunprasath P
7e8b65eb11 dts: arm: microchip: Add DMA node for PIC32CM-JH family devices
Introduce the microchip,dmac-g2-dma.yaml devicetree binding file.
Add the DMA node definition for PIC32CM-JH family devices.

Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
2026-02-28 21:12:52 +01:00
Nicolas Pitre
025375d02f boards: qemu: leon3: pass -m 1G to match DTS SRAM size
The qemu_leon3 DTS declares 1GB of SRAM (reg = <0x40000000 0x40000000>)
but the QEMU command line never specified a -m option, so QEMU used its
default of 128MB.  This mismatch was silently tolerated until now because
nothing validated the heap's end marker beyond physical RAM.

When CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=-1 (the default), the malloc
heap claims the entire declared SRAM (~1GB).  The heap end marker chunk
is written at ~1GB offset from the heap base, well beyond QEMU's 128MB
of physical RAM.  Those writes are silently lost, leaving the end
marker's LEFT_SIZE field as zero.

Commit bec6349cc7 ("lib: heap: introduce SYS_HEAP_HARDENING tiered
Kconfig") made bidirectional size round-trip checks the default when
CONFIG_ASSERT=y (MODERATE level).  The check left_chunk(right_chunk(c))
reads back the end marker's LEFT_SIZE and detects the zero value,
triggering "heap corruption (free chunk linkage)" across many unrelated
tests on this board.

Add -m 1G to the QEMU flags so the emulated RAM matches the declared
DTS size, consistent with how other QEMU boards (arc, riscv32, x86)
already specify their memory.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-28 10:10:18 +01:00
Nicolas Pitre
2d747e55a3 cmake: prohibit LTO for heap_constants.c offsets source
Commit 518d8420c9 ("lib: heap: compute Z_HEAP_MIN_SIZE from actual
struct layouts") added heap_constants.c to the offsets library, but
did not add the prohibit_lto compile option that offsets.c has.
When LTO is enabled, the compiler optimizes away the absolute symbols
emitted by GEN_ABSOLUTE_SYM, causing them to be missing from the
generated offsets.h.  This breaks builds that use Z_HEAP_MIN_SIZE
(via kernel/mempool.c) with LTO-enabled configurations.

Fix by adding heap_constants.c to the same set_source_files_properties
call that disables LTO for offsets.c.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-28 10:10:18 +01:00
Braeden Lane
356f6e9cb9 tests: drivers: dma: cyclic: re-init guard after inter-cycle memset
Commit 7839d958ac ("tests: drivers: dma: cyclic: check rx buf
overflow") added a 16-byte guard region at the end of rx_data,
initialized to 0xA5 before the test starts, with overflow checks
after each cycle.

Between cycle 1 and cycle 2, the test resets the receive buffer with
memset(rx_data, 0, sizeof(rx_data)). Since rx_data was enlarged to
CONFIG_DMA_CYCLIC_XFER_SIZE + GUARD_BUF_SIZE, this zeros the guard
region along with the transfer area. The second cycle's guard check
then finds 0x00 instead of 0xA5 and fails, even though the DMA never
wrote past the buffer.

Fix by re-initializing the guard to 0xA5 immediately after the
inter-cycle memset.

Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
2026-02-27 21:09:33 +00:00
Pete Johanson
4f1956a130 drivers: serial: More complete TX errata fix for MAX32
Some MAX32 targets may fail to raise TX half/almost empty interrupts,
so add an optional workaround for those scenarios to ensure no missed
TX completion when using the interrupt API.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2026-02-27 21:09:31 +00:00
Robert Robinson
edc63785b1 dts: nordic: nrf7120: Update MRAM partitions
MRAM sizes were wrongly defined in .dtsi files and
so required updating.

Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
2026-02-27 21:04:17 +00:00
Robert Lubos
5ab02c7e7a net: ip: Allow to specify default router with net_if_ipv6_router_add()
Align the net_if_ipv6_router_add() behavior with its IPv4 counterpart,
where it is possible to specify whether the router is a default one
instead of making assumptions based on the lifetime value.

The current behavior was likely inspired by the Neighbor Discovery RFC,
where the lifetime parameter of 0 received in the Router Advertisement
message indicates that the router should not be treated as a default
router, however this is an implementation detail of the Neighbor
Discovery protocol and does not need to be enforced at the router API
level, as this can be used outside of this protocol (for example when
router is added manually from the application).

Therefore, allow to specify the "is_default" parameter separately just
like in the IPv4 case.The Router Advertisement handling routine will
just specify the "is_default" value based on the received lifetime
value.

Also, clarify in the function documentation what does it mean to specify
lifetime to 0 (which means the router never expires according to current
implementation).

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2026-02-27 21:03:52 +00:00
Fabian Blatz
24f0e87617 boards: heltec: Remove fb suffix from ssd1306 compatible
Update SSD1306 display controller compatible string from solomon,ssd1306fb
to solomon,ssd1306 to align with the Zephyr 4.4.0 display controller
naming convention.

Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
2026-02-27 21:03:43 +00:00
Grzegorz Chwierut
be78f760e3 tests: twister: Update unit tests after changes in HardwareMap
Updated twister unit tests after refactoring of HardwareMap
class.

Signed-off-by: Grzegorz Chwierut <grzegorz.chwierut@nordicsemi.no>
2026-02-27 21:02:56 +00:00
Grzegorz Chwierut
106ea725a5 twister: Remove redundant DUT storage from classes
Simplify the design by removing the `detected` attribute from
HardwareMap class and DUT storage from ProjectBuilder class.
Instead of storing detected DUTs as instance attributes, pass
them as method parameters where needed.

This eliminates data duplication since ProjectBuilder can access DUTs
directly from the environment object, and HardwareMap doesn't need to
maintain its own copy of detected DUTs. The refactoring makes the code
cleaner and reduces the risk of inconsistent state between different
objects storing the same DUT information.

Signed-off-by: Grzegorz Chwierut <grzegorz.chwierut@nordicsemi.no>
2026-02-27 21:02:56 +00:00
Nicolas Pitre
05828546db samples: mcumgr: smp_svr: disable heap hardening for ram_load variant
The nrf52840dk ram_load variant is very tight on RAM. The MCUboot
RAM_LOAD padding section rounds the image size up to the next
power-of-2 boundary, so even a small increase in code or rodata
can double the padding and overflow the RAM region.

The sys_heap hardening code pushes the image just over the 128KB
boundary, causing padding to jump from 128KB to 256KB and
overflowing RAM by ~55KB.

Disable heap hardening for this build. Since CONFIG_ASSERT is off,
the previous __ASSERT-gated heap checks were inactive anyway, so
HARDENING_NONE preserves the same level of validation.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
b9dd78dc20 tests: drivers: tee: optee: fix heap corruption from RPC buffer overflows
Several test SMC callback handlers request only 1 byte via
OPTEE_SMC_RPC_FUNC_ALLOC but subsequently write a full
struct optee_msg_arg (with params) into the allocated buffer.
This is a heap buffer overflow: struct optee_msg_arg alone is
larger than 1 byte, and the params array extends it further.

For example, cmd_gettime_call case 0 requests 1 byte, then case 1
casts the buffer to struct optee_msg_arg and writes cmd, num_params,
and params[0] — roughly 72 bytes into a 1-byte allocation.

This went unnoticed because nothing validated the heap metadata
after the overflow. The corruption was detected by the new
SYS_HEAP_HARDENING_MODERATE free-list linkage checks introduced in
the sys_heap hardening series: the overflow from the undersized
RPC buffer corrupts adjacent heap chunk headers, which the
allocator now catches at free() time with:

  "heap corruption (free list linkage)"

Fix all 6 affected callbacks to request the correct size using
OPTEE_MSG_GET_ARG_SIZE(num_params):

  cmd_alloc_free_call:  OPTEE_MSG_GET_ARG_SIZE(1) — 1 param used
  cmd_rpc_call:         OPTEE_MSG_GET_ARG_SIZE(2) — 2 params used
  cmd_shm_alloc_appl:   OPTEE_MSG_GET_ARG_SIZE(1) — 1 param used
  cmd_gettime_call:     OPTEE_MSG_GET_ARG_SIZE(1) — 1 param used
  cmd_suspend_call:     OPTEE_MSG_GET_ARG_SIZE(1) — 1 param used
  cmd_notify_alloc_call: OPTEE_MSG_GET_ARG_SIZE(1) — 1 param used

The normal_call callback is not affected: it only performs ALLOC
then FREE without writing any optee_msg_arg into the buffer.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
d1824fa07a lib: heap: validate canaries on free chunk removal
At FULL hardening, trailer canaries on used chunks implicitly guard
adjacent free chunk headers: a sequential buffer overflow must corrupt
the used chunk's trailer before reaching the next header.  However,
when a free neighbor's metadata is needed for merging during free(),
the neighbor's header could already have been corrupted by an overflow
from its left used chunk that hasn't been freed yet.  For example:

  [hdr_U1] [data_U1] [trailer_U1] [hdr_F] [...] [hdr_U2] [trailer_U2]

If data_U1 overflows past trailer_U1 and corrupts hdr_F, freeing U2
would use hdr_F's corrupted size and free-list pointers for merging,
potentially leading to heap structure corruption or arbitrary writes.

Additionally, a corrupted LEFT_SIZE in a used chunk being freed can
point to a fake header crafted inside the left neighbor's data area:

  [hdr_U1] [data_U1 ..fake_hdr.. trailer_U1'] [hdr_U2'] [data_U2] ...
                       |           corrupted   LEFT_SIZE points
                       |           by overflow  to fake_hdr
                       +<--------------------------+

A determined attacker can make fake_hdr's size field self-consistent
with the corrupted LEFT_SIZE so that the structural round-trip checks
pass.  If fake_hdr is marked "used", free_chunk() skips the left
merge and the corruption goes undetected.  If marked "free", it
triggers a bogus merge with attacker-controlled free-list pointers.

Both cases are caught by verifying the left used neighbor's canary:
any overflow from the left must pass through trailer_U1 to reach
hdr_U2's LEFT_SIZE field, so the corrupted canary acts as a tripwire
regardless of whether the resulting fake header is marked used or free.

Address this by introducing free_chunk_check() which validates a free
chunk's structural integrity before trusting its header fields.  It
consolidates the existing MODERATE-level structural checks (chunk
linkage, used-bit consistency) with a new FULL-level canary
verification of the left used neighbor.  Factoring these checks into
a dedicated function lets callers specify @left_trusted according to
context (e.g. the chunk being freed is the left neighbor of the right
merge candidate, so its canary need not be rechecked).

In inplace_realloc()'s shrink path, the freed suffix's left neighbor
is always the chunk being reallocated (used, just validated).  This
path inlines only the right merge to avoid the unnecessary left canary
check.

The check is called before every free list removal: in free_chunk()
for left/right merge candidates, in alloc_chunk() when pulling from
a bucket, and in inplace_realloc() before consuming the right
neighbor.

Also give chunk0 a canary trailer so that the left-neighbor canary
check works uniformly for the first free chunk in the heap.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
9cbe108187 tests: lib: heap: update test variants for hardening levels
Replace canary-specific test variants with hardening level variants:
- hardening_none: verifies zero-overhead path
- hardening_full: exercises canary + all lower-level checks

No extreme variant is added as the tests already perform explicit
heap validation after each operation.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
bec6349cc7 lib: heap: introduce SYS_HEAP_HARDENING tiered Kconfig
Replace the standalone SYS_HEAP_CANARIES bool with a tiered
SYS_HEAP_HARDENING choice controlling runtime validation:

  NONE (0)      - no checks
  BASIC (1)     - double-free and overflow detection in free/realloc
  MODERATE (2)  - free list and neighbor consistency checks
  FULL (3)      - trailer canary on every allocation
  EXTREME (4)   - exhaustive heap validation on every operation

Default is MODERATE when ASSERT is enabled, BASIC otherwise.

Hardening checks are independent of CONFIG_ASSERT: they use
LOG_ERR + k_panic() instead of __ASSERT so the configured level
is always honored regardless of assertion settings.

Also adds heap logging via LOG_MODULE_REGISTER. This paves the way for
eventual permanent debugging instrumentation.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
d7c880c52d lib: heap: extract z_heap_full_check() from sys_heap_validate()
Factor out the core heap validation logic into z_heap_full_check()
which takes a struct z_heap pointer directly. This allows internal
callers (e.g. alloc_chunk) to validate the heap without needing
the public struct sys_heap wrapper.

sys_heap_validate() becomes a thin wrapper that calls
z_heap_full_check() and then validates runtime stats.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00
Nicolas Pitre
39ff3c4863 tests: lib: heap: add test variants for CONFIG_SYS_HEAP_CANARIES
Add canary-enabled test variants to the heap, heap_align, and heap_min
test suites to exercise the heap canary corruption detection feature.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2026-02-27 21:02:45 +00:00