Properly use EUSART1 for the XIAO connector serial device, and switch XIAO
SPI to EUSART0 to allow simultaneous use.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Use the default -1 value for COMMON_LIBC_MALLOC_ARENA_SIZE, i.e. let the
heap expand to the remaining amount of memory.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Updated the PLL input frequency calculation to include
division by the HSI clock divider.
Enable HSI divider using LL_RCC_HSI_EnableDivider().
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Added support for selecting channels A, B, both together, and all channels
on the AD5686 DAC driver. This improves flexibility for multi-channel
DAC applications.
Signed-off-by: Aditya Ganesh <adga5133@colorado.edu>
The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
This change alignes HCI drivers behavior with Host expectation. That is:
if an HCI driver managed to send a packet to Controller, the HCI driver
also unreferences it. If the HCI driver didn't manage to send the
packet to Controller and returns an error code, it does not unreferences
buffer.
This change aligns the behavior of HCI drivers with the Host's
expectations. Specifically:
- If an HCI driver successfully sends a packet to the Controller, the
HCI driver also unreferences it.
- If the HCI driver fails to send the packet to the Controller and
returns an error code, it does not unreference the buffer.
Fixes#94445
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
GCC 14 takes a look these functions which are just 'return true' and
inlines them even though they has the noinline attribute set. This happens
because the compiler computes the possible range of values from the
function call, and as that is a single value (true), it replaces the call
with that value. So it's not strictly inlining the function?
Insist a bit harder by adding a compiler_barrier to the functions which
seems to solve the issue.
Signed-off-by: Keith Packard <keithp@keithp.com>
On arm64, GCC feels free to use floating point registers for essentially
anything unless we build with -mgeneral-regs-only. After the FPU gets used
in an interrupt handler, interrupts are disabled as there's no place to
save the registers during a nested exception. As the C library may be built
separately without this flag, we cannot use any of its functions or risk
having nested exceptions fail.
Switch printk usage to k_str_out and stick to (mostly) Zephyr internal
functions to ensure nested interrupts work correctly.
Signed-off-by: Keith Packard <keithp@keithp.com>
GCC 14.3 will happily delete any code that appears before
__builtin_unreachable that isn't separated with an obvious branch. That
includes __asm__ statements, even those which generate traps.
The failure case that I debugged was on x86 in
z_check_stack_sentinel. There is a store to restore the sentinel to the
correct value just before the ARCH_EXCEPT, and that macro emits 'int $32'
followed by CODE_UNREACHABLE. Because the compiler didn't understand that
ARCH_EXCEPT was changing execution flow, it decided that the sentinel
restoring store 'couldn't' be reached and elided it.
I added the "memory" clobber to the asm statement in ARCH_EXCEPT before
CODE_UNREACHABLE to enforce that all pending store operations be performed
before the asm statement occurs. This ensures that they are not deleted by
the compiler.
I think this might be a GCC bug. The GCC documentation explicitly documents
that asm statements which change the flow of control should be followed by
__builtin_unreachable.
Signed-off-by: Keith Packard <keithp@keithp.com>
Zephyr replaces the toolchain version of stdint.h to define uint32_t and
int32_t as int rather than long. This breaks the ARM MVE intrinics which
require uint32_t to be defined as unsigned long.
Define 'ZEPHYR_USE_TOOLCHAIN_STDINT_H_' as that causes zephyr_stdint.h to
be skipped, ensuring that the normal stdint.h types are used instead.
Signed-off-by: Keith Packard <keithp@keithp.com>
The stm32u3x header files defines LL_ADC_SINGLE_ENDED but not
LL_ADC_DIFFERENTIAL as the device doesn't support differential mode. The
driver only checked for LL_ADC_SINGLE_ENDED and assumed that when that was
defined, LL_ADC_DIFFERENTIAL would also be defined.
Check for both when figuring out which calibration type will be required.
Signed-off-by: Keith Packard <keithp@keithp.com>
When the target has only a single CPU, this function cannot ever
succeed. Skip all of the drama and just return -EINVAL. This makes GCC 14
happy as it doesn't get confused about possible out of bounds access of the
soc_cpus_active array.
Signed-off-by: Keith Packard <keithp@keithp.com>
Add zephyr,pm-device-runtime-auto; to uart135 which is the uart
used for logging to enable PM_DEVICE_RUNTIME for it, which is
required for its power domains.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Check if cqe is NULL before accessing cqe->result in
spi_rtio_transceive(). Prevents possible null pointer dereference
from rtio_cqe_consume() return value.
CID: 516229
Fixes: #90547
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Adds an overlay to enable the GPIO api tests to run on the
kit_psc3m5_evk board. GPIO 3.0 is used as an output, 3.1 is used as an
input for the test. The test expects GPIO 3.0 and GPIO 3.1 to be
jumpered together.
Signed-off-by: John Batch <john.batch@infineon.com>
1. Renamed MCXA276 to MCXA266
2. NXP frdm_mcxa276 is renamed to frdm_mcxa266,
add this information to migration-guide-4.3.rst.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
1. Renamed MCXA166 to MCXA346.
2. NXP frdm_mcxa166 is renamed to frdm_mcxa346,
add this information to migration-guide-4.3.rst.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. Add core_id for RT685 HIFI4 core, this variable is
used in MCUX SDK cmake.
2. Set cmake variables 'CONFIG_MCUX_COMPONENT_driver.smartdma_mcxn'
and 'CONFIG_MCUX_COMPONENT_driver.smartdma_rt500' to "ON" as these
variables control the loading of source files in the latest driver
CMakeList.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Now use the 5-parameter function "PINT_PinInterruptConfig"
deprecated in MCUX SDK, need to add compile definition
'PINT_USE_LEGACY_CALBACK' to make intc_nxp_pint compatible
with updated 'fsl_pint' driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
'MCUX_HW_CORE' and 'MCUX_HW_FPU_TYPE' are used in
modules/hal_nxp/device.cmake. It is a variable used
by MCUX SDK CMake.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
remove spi_cs_is_gpio checks before
spi_context_cs_control, as it is also done
inside and we don't need to check two times.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The uart_stm32 driver gives no way for a user to
tell if setting a new baud rate was successful.
Propagate error checks up to the API level.
Signed-off-by: Eden Frosst <edenfrosst@gmail.com>
The SAMPLERATE register can be used as a local timer instead
of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set
to Timers, it is sufficient to trigger SAMPLE task only once in order
to start the SAADC and triggering the STOP task will stop sampling.
The SAMPLERATE.CC field controls the sample rate.
The SAMPLERATE timer should not be combined with SCAN mode and
only one channel should be enabled when using the internal timer.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The stm32n6 features an RNG block. The RNG is a true NIST SP800-90B
compliant entropy source according to the stm32n657x0 reference manual[1].
Per Table 3 in the reference manual, the RNG peripheral register boundary
address (secure) is 0x54020000 to 0x540203FF. That is, base address
0x54020000 and size 0x400.
Per Table 73 in the reference manual, the RNG peripheral has only a single
rng_clk option (hsis_osc_ck).
Per section 14.10.66 (and more) the RNG peripheral control is performed
through AHB3 using bit 0.
As such, the `clocks` property contains a single phandle to the RCC AHB3
bit 0 entries.
Per Table 135 in the reference manual, the RNG peripheral interrupt is
located at position 40 in the NVIC.
[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
stm32 smbus driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 sdhc driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 i3c driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dwmac_stm32h7x driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 mco clock driver is relying on the pinctrl framework
for configuring the MCO pin hence select CONFIG_PINCTRL
to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 crypto driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 ltdc driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 mipi dsi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmipp driver requires a reset control and pinctrl
(depending on the configuration) hence ensure that
CONFIG_RESET and CONFIG_PINCTRL are properly selected to allow
proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Ensure NSBank values are validated at build time.
That helps to identify and fix incorrect bank values.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
