The commit 1fe332de61 moved the maintainer
file check step from a standalone workflow to the assigner workflow, which
uses the `action-python-env` action to install the Python requirements.
The version of PyGithub package installed by the `action-python-env` action
in the assigner workflow is 2.6.1, which is older than the minimum required
version 2.7.0 (see 5a4b0ac4d7 for more
details), and this caused the maintainer file check to erroneously flag the
users with "Triage" role.
This commit updates the assigner workflow to use the
action-python-env@32e53bef090c33d53aa94f1d9a9d29c93cfdc5f7, the latest
version at the time of this change with up-to-date requirements file, in
order to ensure that PyGithub>=2.7.0 is installed.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
It seems the new microvolt/microamp rework (#95588) simply forgot to
implement zero current voltage offsets.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
Due to slight differences in the way that LLVM and GNU linkers work,
the call to `z_stack_space_get()` is not dead-stripped when linking
with `lld` but it is dead-stripped when linking with GNU `ld`.
The `z_stack_space_get()` function is only available when
`CONFIG_INIT_STACKS` and `CONFIG_THREAD_STACK_INFO` are defined.
The issue is reproducible (although requires building LLVM and
setting up some environment variables) and goes away with the proposed
workaround.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Drop the "area: Sensors" label from Wurth and TDK sensor areas, the
current setup is causing the issue assigner script to pick up those
maintainers for any issue labeled as sensor as it does not know better,
if these areas wants a label for issue tracking their maintainer can
make an area specific one and use it.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
FVP's (ARM Fixed Virtual Platform) atomic instruction emulation appears
to not properly implement the cache coherency guarantees specified by the
ARM architecture. Atomic instructions with acquire/release semantics (LDAR,
LDAXR, LDADDAL, etc.) should ensure that loaded values reflect any prior
stores from other CPUs, but on FVP this can fail, leading to stale cached
values being read in SMP configurations.
This manifests as performance issues in lockfree data structures as
demonstrated by tests/lib/lockfree hanging with excessive retries.
This commit adds board-specific atomic operation implementations with
explicit (and, in theory, redundant) data memory barrier (DMB SY)
instructions before all operations that read from memory. These barriers
force cache invalidation before reads, working around the FVP issue by
ensuring CPUs observe the latest values written by other CPUs. This
should be temporary until this FVP situation is better understood/fixed.
Note: FVP's cache_state_modelled parameter can improve the lockfree test
outcome but this is also 10x slower or more with many tests.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Increase FVP Base RevC 2xAEM DRAM from 2 MB to 128 MB to match the
platform's actual capabilities and align with QEMU's configuration.
The FVP Base RevC supports ~4 GB of RAM as documented in the Linux
kernel device tree (arch/arm64/boot/dts/arm/fvp-base-revc.dts), which
defines two memory regions totaling approximately 4 GB.
The previous 2 MB limitation caused issues with demand paging tests
where the kernel VM size (8 MB) exceeded available RAM, triggering
early page faults before the page frame allocator was initialized.
With 128 MB, demand paging workloads have sufficient memory to operate
without premature paging.
This change brings FVP's memory configuration in line with QEMU
Cortex-A53 (128 MB).
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Memory protection and userspace tests require more MMU translation
tables than the default. Without this increase, tests fail with:
E: CONFIG_MAX_XLAT_TABLES too small
ASSERTION FAIL [ret == 0] @ arch/arm64/core/mmu.c:1244
privatize_page_range() returned -12
Increase defaults when both USERSPACE and TEST are enabled:
- 32 tables for SMP configurations
- 24 tables for non-SMP configurations
This fixes:
- sample.kernel.memory_protection.shared_mem (all platforms)
- rtio.api.userspace (v8a, v9a)
- rtio.api.userspace.submit_sem (v8a, v9a)
- portability.posix.common.userspace
Consequently the demand paging test needed adjustment to its
qemu_cortex_a53 configs to keep working as this test is highly
sensitive to the amount of available free memory.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Increase ARM64 stack sizes to accommodate deeper call stacks in
userspace and SMP configurations when FPU_SHARING is enabled:
- PRIVILEGED_STACK_SIZE: 1024 → 4096 bytes (with FPU_SHARING)
- TEST_EXTRA_STACK_SIZE: 2048 → 4096 bytes (with FPU_SHARING)
The default 1KB privileged stack is insufficient for ARM64 userspace
syscalls when FPU context switching is enabled.
Symptom: Userspace tests crash with Data Abort (EC 0x24) near stack
boundaries during syscalls, particularly on SMP configurations where
multiple threads exercise FPU lazy switching.
Fixes previously failing CI test on fvp_base_revc_2xaem SMP variants:
- kernel.threads.dynamic
- Multiple userspace tests with FPU_SHARING enabled
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add stress test for SIMD register save/restore during context switching.
The test validates correct FPU context handling using either ARM Neon or
SVE2 instructions depending on the build target.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Expand the SVE context switching test to cover all thread privilege
combinations with validation of SVE state preservation across different
contexts.
Test Coverage:
- Privileged vs Privileged threads (kernel mode)
- User vs User threads (userspace with memory domains)
- User vs Privileged threads (mixed privilege levels)
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add test to validate SVE (Scalable Vector Extension) context switching
implementation, ensuring proper register preservation across thread
switches in multi-threaded environments.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Implement Scalable Vector Extension (SVE) context switching support,
enabling threads to use SVE and SVE2 instructions with lazy context
preservation across task switches.
The implementation is incremental: if only FPU instructions are used
then only the NEON access is granted and preserved to minimize context
switching overhead. If SVE is used then the NEON context is upgraded to
SVE and then full SVE access is granted and preserved from that point
onwards.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This fixes the following:
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:7
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:22
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:28
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:38
Column:Remove space before '(' in if() statements
CMakeStyle File:cmake/gcc-m-cpu.cmake Line:48
Column:Remove space before '(' in if() statements
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A
specific configuration parameters.
New board target:
- fvp_base_revc_2xaem/a320
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
ARMv9-A is AArch64-only and does not support AArch32 execution states
at EL1/EL2/EL3. Configure TF-A build to disable AArch32 register
context (CTX_INCLUDE_AARCH32_REGS=0) when building for ARMv9-A platforms.
This fixes TF-A boot failures on ARMv9-A non-secure variants where
TF-A would panic with:
ERROR: EL1 supports AArch64-only. Please set build flag
CTX_INCLUDE_AARCH32_REGS = 0
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add ARMv9-A architecture support with Cortex-A510 CPU as the default
processor for generic ARMv9-A targets.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add deprecated.cmake mappings to redirect old board names to new
unified structure:
- fvp_base_revc_2xaemv8a
→ fvp_base_revc_2xaem/v8a
- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp
→ fvp_base_revc_2xaem/v8a/smp
- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
→ fvp_base_revc_2xaem/v8a/smp/ns
This ensures existing build commands and documentation continue to work
with deprecation warnings while transitioning to the new board structure.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Create unified board configuration to replace verbose board naming
with shorter hierarchical structure. This board works with the new
unified fvp_aem SOC series and supports the v8a architecture variant.
This enables board targets like:
- fvp_base_revc_2xaem/v8a (basic ARMv8-A)
- fvp_base_revc_2xaem/v8a/smp (ARMv8-A SMP)
- fvp_base_revc_2xaem/v8a/smp/ns (ARMv8-A SMP non-secure)
This structure replaces the existing overly verbose board designations
with a cleaner, more maintainable organization and provides a foundation
for adding v9a variants.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Reorganize fvp_aemv8a SOC into unified fvp_aem series with a v8a
architecture variants to enable cleaner board target naming. This also
sets the stage for upcoming ARMv9-A support.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This adds necessary configuration files to build with SMP and no trusted
firmware. Given PSCI is not available, CPU power management uses the FVP
power controller directly. This simplifies debugging, and builds faster
too!
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add a new PM CPU ops driver for Arm Fixed Virtual Platform (FVP) that
enables bare metal SMP support without Arm Trusted Firmware (ATF).
The driver provides CPU power-on and system reset operations by directly
interfacing with FVP's power controller (PWRC) and V2M system registers.
The implementation includes RVBAR_EL3 configuration to redirect
secondary CPU reset vectors to Zephyr's image header, enabling
proper SMP initialization without firmware assistance.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Add initial support for the Waveshare RP2350-Zero, a low-cost,
high-performance Pico-like development board based on the Raspberry
Pi RP2350A microcontroller.
This commit introduces the board definition, devicetree files, pin
control configuration, Kconfig options, and board documentation.
The RP2350-Zero’s Arm and RISC-V cores are supported with this
port. Basic peripherals (GPIO, UART, I2C) are configured and
tested. Verified by building and running the Zephyr "hello_world"
sample on the RP2350-Zero / RP2350-One boards, and manually testing
the GPIO, I2C, PIO, and RGB LED.
Signed-off-by: Stephano Cetola <stephanoc@gmail.com>
Adds overlays to enable test runs for DMA on the following tests:
-tests/drivers/dma/chan_blen_transfer
-tests/drivers/dma/loop_transfer
Signed-off-by: John Batch <john.batch@infineon.com>
Adds USE_INFINEON_LEGACY_HAL kconfig option to the PSOC6, CYW920829, and
xmc7200 series SOCs. These devices have not transitioned to newer HAL
based drivers yet.
Signed-off-by: John Batch <john.batch@infineon.com>
Updates DMA includes from the modules needed for DMA PDL based driver
implementation.
Cleans up cmake to use only USE_INFINEON_DMA Kconfig option to select
dma files from PDL/HAL.
Signed-off-by: John Batch <john.batch@infineon.com>
Some FlexCAN devices have enhanced bit timing registers (EPRS ENCBT EDCBT)
with extended timing configuration ranges and different behavior compared
to standard bit timing registers.
This change adds proper support for these enhanced registers, utilize full
bit timing capabilities.
Key differences for enhanced bit timing registers:
- Extended timing ranges with larger maximum values for sjw, phase_seg1,
phase_seg2, and prescaler fields
- No propagation segment configuration support, so prop_seg must be 0
- prop_seg value is used directly without the typical 'minus 1' adjustment
The implementation adds conditional compilation based on the
`FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG` feature flag.
For Enhanced registers, use extended timing limits and prop_seg directly.
Test this commit on mimxrt1180_evk/mimxrt1189/cm33 drivers.can.timing
test case, and enable `TEST_ALL_BITRATES` Kconfig symbol.
Signed-off-by: William Tang <william.tang@nxp.com>
File groups inherit file patterns from their parent area. A file will only
match a file group if it first matches the parent area's patterns, and then
also matches the file group's own patterns. This allows file groups to
further filter and subdivide files that are already covered by the area.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This new section allows defining a group of files in an area and makes
it possible to assign collaborators to the file group being defined.
The purpose of this new section is to allow fine tuning who is added as
reviewer when files change in a group. It is especially useful in large
areas with hundreds of files, for example platform areas.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A low-load period that is too short (1ms) will cause
the average load to remain almost unchanged. Increase
it to 100ms.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
