Add the ESP-AT command driver (drivers/wifi/esp_at) under the
Espressif Platforms section to ensure proper maintainer coverage.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Add a board-specific devicetree overlay
to support the GPIO basic API test.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Add a board-specific devicetree overlay to enable
the PWM API test suite.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Default disable dac1 and fdcan3 nodes in stm32h5f5j_dk board since they
respectively conflict with the pin muxing for spi1 and adc3.
Add a board overlay file for DAC driver tests and samples to enable
dac1 and disable spi1.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Rename stm32h5e/h5f SRAMs node labels in the SoC DTSI files to better
match the SRAMs names in the literature.
Update stm32h5f5j_dk board accordingly.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Restore the UART9 node on the stm32h5e/f series.
The instance exists like on other stm32h5 devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This allows to tune L2CAP RTX timer value for L2CAP connection
requests. Allowed range is 1-60 seconds while defaults to 40.
Since this is mainly useful for BI (behavior invalid) qualification
tests allows to tune it only if BT_TESTING is selected.
This is required for running L2CAP/COS/CED/BI-29-C qualification
test in reasonable time since it requires 255 iterations of
failed (timed out) connection requests.
Signed-off-by: Szymon Janc <szymon.janc@codecoup.pl>
The error log was obvisouly copied from previous lines, fixing the error
log when adding the ca certificate fails.
Signed-off-by: Joel Guittet <jguittet@witekio.com>
Use the new has-injected-support property in the Kconfig instead of
filtering on series directly, and use it also in the driver to return an
error if a specific instance doesn't support injected (this is the case
for STM32U5 where ADC1 and 2 support injected, but not ADC4).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 ADC instances that support the injected channel feature, add
the newly created property to indicate that.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a property to the STM32 ADC bindings to indicate whether the ADC
instance supports the injected channel feature.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a test for injected channels. The test first starts a regular
asynchronous sampling of several channels, then starts an injected
sampling. The test checks that both the regular and injected samplings
run without issues.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add injected mode support for STM32 Vref sensor.
When in injected mode, this configures the sensor channel and sensor enable
bit at start to prevent any conflict later: some registers can't be written
while a conversion is on-going.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add injected mode support for STM32 Vbat sensor.
When in injected mode, this configures the sensor channel and sensor enable
bit at start to prevent any conflict later: some registers can't be written
while a conversion is on-going.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add injected mode support for STM32 temperature sensor.
When in injected mode, this configures the sensor channel and sensor enable
bit at start to prevent any conflict later: some registers can't be written
while a conversion is on-going.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In order to write into some ADC registers, it is necessary to have no
on-going conversions (either regular, injected, or both). Until now, each
time such a write was needed, the ADC was disabled unconditionally,
stopping any potential on-going conversion.
With the introduction of the injected mode, this could lead to problems
if for example an injected is configured differently than a running
regular one. In that case it would stop the regular conversion. If the
application is waiting the result before starting another one, it will be
stuck waiting forever.
To avoid cases like this, return an error rather than stopping conversion
and disabling the ADC. This reworks many functions to return an error in
case it was not possible to safely disable the ADC.
It stays possible to force an ADC disable even though a conversion is
running, this is useful at init where we don't want this to fail.
This also creates a dedicated function for the preselection register to
avoid duplication.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add injected mode support for STM32 ADC driver. To avoid potential
conflicts when configuring the ADC registers, some settings (like presel)
are moved into the channel_setup function when injected is enabled.
Also configures an ISR when DMA and injected mode are enabled. The reason
is that DMA is not available for injected sequence, so an ISR is still
necessary in this case.
Factorizes the "start_read_xxx" functions to avoid needless duplication
between sync/async and regular/injected mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add sequence priority support in the ADC API.
The priority assigned to a sequence reflects how time-sensitive it is
compared to other sequences. The number of priority levels supported
and the exact behavior obtained by assigning a specific priority to a
sequence are hardware-specific.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add SPI, I2C, ADC, counter, watchdog, PWM, and flash to the
supported features in board YAML.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
The runner always selected elf_file, ignoring hex_file and bin_file from
RunnerConfig. This broke MCUBoot support since the bootloader
requires hex/bin format and the build system sets hex_file to
signed images (zephyr.signed.hex).
Fixes commit 3c7d973 ("west: runners: probe-rs: Add enhanced
functionality")
Signed-off-by: Michał Bogdziewicz <michal@bogdziewicz.xyz>
The arch.interrupt.gen_isr_table_local.riscv test requires
CLIC/PLIC to work correctly. Since SweRV series SoCs do not
have CLIC/PLIC, the tests cannot run at this point. So skip
these tests for now so CI won't report failures on these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Shorten the delay to run the syscall stress test on whisper
simulator, as simulator is a lot slower compared to real
hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The whisper simulator does not have a working implementation
for wfi instruction and simply treats it as no-op. Therefore,
any CPU idle test will fail as wfi returns immediately. So
skip those tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Whisper simulator does not support writing to MIP register
to trigger interrupts. Also the external PIC interrupt
controller also do not support manually triggering
interrupts. So exclude these platforms from the shared
interrupt tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Extend the cdns_swerv/s400 board to test PMP capability on
whisper. Although S400 technically does not advertise PMP
support, we are simply using it as a base to make sure PMP
works.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds support for Cadence SweRV S420 SoC which is similar
to S400 but with support for 2 threads.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the bits to support running whisper as simulator
so that we can do west build with debug and run targets.
The simulator is used for simulating SweRV SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a very simple output only console driver for
the consoleio provided by Whisper ISS for simulating
SweRV SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
...relying on direct pointer access. This avoids compiler
complain about casting to pointer from integer of
different size.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is a macro RISCV_MAX_GENERIC_IRQ in the code which is not
defined anywhere. The assumption is that this would come from
the SoC configuration. However, since we have been moving away
from including soc.h in drivers, instead we introduce another
kconfig CONFIG_SWERV_PIC_MAX_GENERIC_IRQ for this.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SweRV naming is under Cadence now so rename to have
a proper vendor prefix, and removes the EH1 naming as
this can be used for multiple family of SoCs.
The old compatible "swerv,pic" can still be used but
cannot be used together with "cdns,swerv-pic".
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add missing notification clearing for the GTBS instance
in the disconnected callback.
Fixes#104568
Signed-off-by: Maximilian Zimmermann <gitmz@posteo.de>
If the client removes its subscription to any of the TBS
characteristics at any time, the pending appropriate flags
are now being cleared.
Fixeszephyrproject-rtos/zephyr#104511
Signed-off-by: Hanliang Xu <leonxu2004@outlook.com>
This removes dead code. Since bt_bap_stream_detach sets
stream->ep = NULL then the call to bt_bap_stream_iso_chan_get
will always return NULL since stream->ep is NULL, and thus
the call to bt_bap_stream_disconnect would always be a no-op.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
